Improving the performance of transmission gate and hybrid CMOS Full Adders in chain and tree structure architectures

Mewada, Manan; Zaveri, Mazad; Thakker, Rajesh A.

doi:10.1016/j.vlsi.2019.09.002

Cited by 14 publications

(5 citation statements)

References 12 publications

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“…The ferroelectric material's non-stable NCE requires careful CFE-tounderlying MOSFET capacitance matching for NCFET performance [27]. NCFET transistors use a ferroelectric (FE) layer in the transistor gate stack to function at lower VDDs while retaining switching speed [28], [29]. The NCFET's threshold voltage, drain current, and device parameters are provided in (3), (4), and Table 3.…”

Section: Related Workmentioning

confidence: 99%

Role of tuning techniques in advancing the performance of negative capacitance field effecting based full adder

Daniel,

Prasad,

Chaturvedi

et al. 2024

IJRES

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<p>The increasing demand for faster, robust, and efficient device development of enabling technology to mass production of industrial research in circuit design deals with challenges like size, efficiency, power, and scalability. This paper, presents a design and analysis of low power high speed full adder using negative capacitance field effecting transistors. A comprehensive study is performed with adiabatic logic and reversable logic. The performance of full adder is studied with metal oxide field effect transistor (MOSFET) and negative capacitance field effecting (NCFET). The NCFET based full adder offers a low power and high speed compared with conventional MOSFET. The complete design and analysis are performed using cadence virtuoso. The adiabatic logic offering low delay of 0.023 ns and reversable logic is offering low power of 7.19 mw.</p>

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Section: Related Workmentioning

confidence: 99%

Role of tuning techniques in advancing the performance of negative capacitance field effecting based full adder

Daniel,

Prasad,

Chaturvedi

et al. 2024

IJRES

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Section: Background Of Counter Cellsmentioning

confidence: 99%

“…In these cells, all input bits have the same weight (2 0 ) which can produce three equivalent bits with different weights (2 0 , 2 1 , and 2 2 ) for the next stage. Based on Equation (1), counter circuits can be classified into two categories, saturated and unsaturated. If the number of inputs is equal to a maximum number of bits, which can be represented by output bits, the cell is a saturated one like 3:2 and 7:3, while the 5:3 is an unsaturated counter.…”

Section: Background Of Counter Cellsmentioning

confidence: 99%

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Voltage over‐scaling CNT‐based 8‐bit multiplier by high‐efficient GDI‐based counters

Sadeghi

Shiri

Rafiee

et al. 2022

IET Computers & Digital Tech

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A new low-power and high-speed multiplier is presented based on the voltage over scaling (VOS) technique and new 5:3 and 7:3 counter cells. The VOS reduces power consumption in digital circuits, but different voltage levels of the VOS increase the delay in different stages of a multiplier. Hence, the proposed counters are implemented by the gate-diffusion input technique to solve the speed limitation of the VOS-based circuits. The proposed GDI-based 5:3 and 7:3 counters save power and reduce the area by 2x and 2.5x, respectively. To prevent the threshold voltage (V th ) drop in the suggested GDIbased circuits, carbon nanotube field-effect transistor (CNTFET) technology is used. In the counters, the chirality vector and tubes of the CNTFETs are properly adjusted to attain full-swing outputs with high driving capability. Also, their validation against heat distribution under different time intervals, as a major issue in the CNTFET technology is investigated, and their very low sensitivity is confirmed. The low complexity, high stability and efficient performance of the presented counter cells introduce the proposed VOS-CNTFET-GDI-based multiplier as an alternative to the previous designs. K E Y W O R D S CNTFET, digital counter, gate-diffusion input (GDI), heat distribution, voltage over-scalingThis is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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“…Over the whole input voltage range, TG provides a low resistance path between the input and output terminals. When combined, NMOS and PMOS transistors propagate logic values without experiencing a threshold voltage drop since their gate terminals are controlled by complementary signals [10]. The TG transmits specific input signals to the output according to the voltage provided to the gate input [11].…”

Section: Introductionmentioning

confidence: 99%

A new Excess-1 circuit based High-Speed Carry Select Adder in 18 nm FinFET Technology

Battini

PASHYA

Sivani

2023

Preprint

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Conventional carry select adder (CCSA) uses a multiplexer in the final stage to select either an excess-1 result or a normal result. To improve the delay and number of transistors a new topology is Proposed (PCSA) that uses only a single type of cell i.e., a 2 − 1 multiplexer. The 2 − 1 multiplexer is constructed in CMOS and TGL logic styles using 18nm FinFETs. The sub-blocks such as half adder and excess-1 circuit used in this PCSA is realized using only a 2:1 multiplexer. Due to the usage of a single type 2:1 multiplexer, the PCSA exhibits better circuit regularity. The new topology of PCSA is designed using FinFET-based TGL and CMOS styles. All the adders such 4- and 8-bit are designed, simulated, and analyzed using Cadence Virtuoso, ADEL, and ADEXL at 18nm FinFET technology. The result analysis reveals that the speed performance and the number of transistors of 8-bit PCSA are better by 44.02% and 4% respectively compared to existing adders.

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Improving the performance of transmission gate and hybrid CMOS Full Adders in chain and tree structure architectures

Cited by 14 publications

References 12 publications

Role of tuning techniques in advancing the performance of negative capacitance field effecting based full adder

Role of tuning techniques in advancing the performance of negative capacitance field effecting based full adder

Voltage over‐scaling CNT‐based 8‐bit multiplier by high‐efficient GDI‐based counters

A new Excess-1 circuit based High-Speed Carry Select Adder in 18 nm FinFET Technology

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