Improving the Performance of WCET Analysis in the Presence of Variable Latencies

Abstract

Due to the dynamic behaviour of acceleration mechanisms such as caches and branch predictors, static Worst-Case Execution Time () analysis methods tend to scale poorly to modern hardware architectures. As a result, a tradeo must be made between the duration and the precision of the analysis, leading to an overestimation of the bounds. This in turn reduces the schedulability and resource usage of the system. In this paper we present a new data structure to speed up the analysis: the eXecution Decision Diagram (), which is an ad-hoc extension of Binary Decision Diagrams tailored for analysis problems. We show how s can be used to represent eciently execution states and durations of instruction sequencesn a modern hardware platform. We demonstrate on realistic applications how the use of an substantially increases the scalability of analysis.

A Framework for Calculating WCET Based on Execution Decision Diagrams

“…In [2], we prove that xdd calculation is equivalent to symbolic representation. Moreover we show how the xdd implementation can be improved (a) by equipping each node with max and min values of their leaves to cut some calculations, (b) by using memoization of intermediate calculation results and (c) by selecting an adapted event order.…”

“…We used an order based on the address of the instructions hosting the event. A precise discussion about this order can be found in [2].…”

The Role of Causality in a Formal Definition of Timing Anomalies

“…We also need runtime information such as the actual instant of each event and the actual order imposed by contention (the EG uses undirected arcs in this case). Bai et al extend the EG with a more compact but equivalent symbolic data structure called Execution Decision Diagram [23]. Hahn et al [1] use microarchitectural execution graphs to represent possible durations between events of interest.…”