Improving the quantum cost of reversible Boolean functions using reorder algorithm

Ahmed, Taghreed; Younes, Ahmed; Elsayed, Ashraf

doi:10.1007/s11128-018-1874-1

Cited by 7 publications

(1 citation statement)

References 17 publications

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“…Dengli et al proposed an improved KFDD based reversible circuit synthesis method [7]. Ahmed et al suggested a synthesis approach using reorder algorithm [8]. Basak et al presented an algorithm using the ESOP expressions [9].…”

Section: -Backgroundmentioning

confidence: 99%

ARASP: An ASIP Processor for Automated Reversible Logic Synthesis

Kalantari¹,

Gerami²,

Eshghi³

2022

jist

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Reversible logic has been emerged as a promising computing paradigm to design low power circuits in recent years. The synthesis of reversible circuits is very different from that of non-reversible circuits. Many researchers are studying methods for synthesizing reversible combinational logic. Some automated reversible logic synthesis methods use optimization algorithms Optimization algorithms are used in some automated reversible logic synthesis techniques. In these methods, the process of finding a circuit for a given function is a very time-consuming task, so it"s better to design a processor which speeds up the process of synthesis. Application specific instruction set processors (ASIP) can benefit the advantages of both custom ASIC chips and general DSP chips. In this paper, a new architecture for automatic reversible logic synthesis based on an Application Specific Instruction set Processors is presented. The essential purpose of the design was to provide the programmability with the specific necessary instructions for automated synthesis reversible. Our proposed processor that we referred to as ARASP is a 16-bit processor with a total of 47 instructions, which some specific instruction has been set for automated synthesis reversible circuits. ARASP is specialized for automated synthesis of reversible circuits using Genetic optimization algorithms. All major components of the design are comprehensively discussed within the processor core. The set of instructions is provided in the Register Transform Language completely. Afterward, the VHDL code is used to test the proposed architecture.

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Section: -Backgroundmentioning

confidence: 99%