Improving the Realization of Multiple-Control Toffoli Gates Using the NCVW Quantum Gate Library

Biswal, Laxmidhar; Bandyopadhyay, Chandan; Wille, Robert; Drechsler, Rolf; Rahaman, Hafizur

doi:10.1109/vlsid.2016.23

Cited by 9 publications

(6 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It is a set of universal transversal primitive gates, which contains CNOT‐gate with 1‐qubit H‐gate, S‐gate, Pauli (X, Y, Z) ‐gate, and non‐Clifford T‐gate [22]. Any design on NCV gate library [23] can be mapped to the Clifford + T‐group by using the identities presented in Figure 1. This NCV gate library was provided by Barenco et al .…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Fault‐tolerant quantum implementation of conventional decoder logic with enable input

Biswal

Mondal

Rahaman

2021

IET Circuits, Devices & Syst

Self Cite

View full text Add to dashboard Cite

Decoherence is the greatest obstacle to the physical realization of scalable quantum computer, jeopardises coherent superposition of the qubit, and makes qubit extremely fragile. Quantum Error Correction Code (QECC), and Fault-tolerant quantum computation collectively could protect qubit and improve scalability. On the other hand, the conventional logic circuit is no more useful in quantum computing due to much difference from quantum logic. However, quantum computer has to perform classical tasks which can be addressed by translating to its equivalent quantum algorithm. Herein, zerogarbage-based reversible and fault-tolerant quantum circuit for 1 : 2, and 2 : 4 Decoder with enable signal using Clifford + T-group are proposed. Further, the design approach to implement n : 2 n decoder on fault-tolerant quantum logic in linear T − depth is extended. Besides, performance parameters likely T − count, T − depth, and garbage output have been evaluated for n : 2 n decoder. This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

show abstract

Section: Introductionmentioning

confidence: 99%

“…[22]. Any design on NCV gate library [23] can be mapped to the Clifford + Tgroup by using the identities presented in Figure 1. This NCV gate library was provided by Barenco et al [24].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Fault‐tolerant quantum implementation of conventional decoder logic with enable input

Biswal

Mondal

Rahaman

2021

IET Circuits, Devices & Syst

Self Cite

View full text Add to dashboard Cite

show abstract

“…The integration and optimization of quantum circuits is of great significance [1] [2] [3]. In recent years, the Clifford + T gates [4] [5] [6] have been used in some typical quantum circuits. Due to the importance of fault tolerance in quantum computing [7] [8], and the fault-tolerant implementation cost of T gates may exceed the implementation cost of Clifford Gate by 100 times or more [4].…”

Section: Introductionmentioning

confidence: 99%

“…In recent years, the Clifford + T gates [4] [5] [6] have been used in some typical quantum circuits. Due to the importance of fault tolerance in quantum computing [7] [8], and the fault-tolerant implementation cost of T gates may exceed the implementation cost of Clifford Gate by 100 times or more [4]. Therefore, minimizing the number of T gates is critical to optimizing the T depth of a quantum circuit.…”

Section: Introductionmentioning

confidence: 99%

The Mapping and Optimization Method of Quantum Circuits for Clifford + T Gate

He¹,

Guan²,

Ding³

2019

JAMP

View full text Add to dashboard Cite

In order to solve the fault tolerance and reliability problems of quantum circuit, a series of structural equivalence rules and optimization operation strategies of quantum circuit are proposed to minimize the number of T gates, increase T gate depth, minimize circuit level, reduce fault tolerance implementation costs and increase circuit reliability. In order to satisfy the nearest neighbor constraints of some quantum systems, a LNN (linear nearest neighbor) arrangement algorithm based on Clifford + T gate quantum circuit is presented. Experiments are done on some benchmarks of RevLib, the results show that the optimization rate of most functions and the running time of the algorithm are better than those of the existing literature.

show abstract

A new design of parity preserving reversible Vedic multiplier targeting emerging quantum circuits

Noorallahzadeh

Mosleh

Ahmadpour

et al. 2023

Int J Numerical Modelling

View full text Add to dashboard Cite

Reversible logic is used increasingly to design digital circuits with lower power consumption. The parity preserving (PP) property contributes to detect permanent and transient faults in reversible circuits by comparing the input and output parity. Multiplication is also considered one of the primary operations in both digital and analog circuits due to its wide applications in digital signal processing and computer arithmetic operations. Accordingly, Vedic mathematics, as a set of techniques sutras, has become popular and is extensively used to solve mathematical problems more efficiently and faster. This work proposes three PP reversible blocks, N1, N2, and N3, which are used to develop a novel effective 2‐bit PP reversible Vedic multiplier and 4‐bit ripples carry adders (RCAs). Moreover, 2‐bit Vedic multiplier and RCA are used to develop the 4‐bit PP reversible Vedic multiplier. The proposed designs outperform the most relevant state‐of‐the‐art structures in terms of garbage output (GO), constant input (CI), gate count (GC), and quantum cost (QC). Average savings of 22.37%, 35.44%, 35.44%, and 34.76%, and 17.76%, 26.60%, 24.52%, and 27.27% respectively, are observed for two‐bit and four‐bit PP reversible Vedic multipliers in terms of QC, GO, CI and GC as compared to previous works.

show abstract

Improving the Realization of Multiple-Control Toffoli Gates Using the NCVW Quantum Gate Library

Cited by 9 publications

References 4 publications

Fault‐tolerant quantum implementation of conventional decoder logic with enable input

Fault‐tolerant quantum implementation of conventional decoder logic with enable input

The Mapping and Optimization Method of Quantum Circuits for Clifford + T Gate

A new design of parity preserving reversible Vedic multiplier targeting emerging quantum circuits

Contact Info

Product

Resources

About