Improving the test quality for scan-based BIST using a general test application scheme

Tsai, Huan-Chih; Cheng, Kwang-Tin; Bhawmik, Sudipta

doi:10.1145/309847.310050

Cited by 19 publications

(24 citation statements)

References 7 publications

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“…It has been shown that applying different numbers (k) of capture cycles after each scan sequence (k captures per scan) can produce patterns with different signal probability profiles at the scan flip-flops [19]. Patterns which matches a specific signal probability profile can improve the detection for some stuck-at faults but deteriorate the detection for others comparing to the pseudo random patterns.…”

Section: A Path Delay Faults Testing For Scan-based Bistmentioning

confidence: 99%

“…Patterns which matches a specific signal probability profile can improve the detection for some stuck-at faults but deteriorate the detection for others comparing to the pseudo random patterns. In order to increase the overall circuit random testability, in [19] the entire test process is divided into multiple test sessions. In each test session, patterns with a specific signal probability profile are generated by applying a unique number of capture cycles after each scan sequence.…”

Section: A Path Delay Faults Testing For Scan-based Bistmentioning

confidence: 99%

“…The response captured at time T k·1 will eventually be scanned out and observed. As noted in [19], applying multiple capture cycles can improve the detection for only a subset of faults. Thus, they found the best number of capture cycles for each fault explicitly by computing the fault detection probability and then identify the number of test sessions and the corresponding number of capture cycles used in each test session.…”

Section: A Path Delay Faults Testing For Scan-based Bistmentioning

confidence: 99%

“…At the end of this run, we obtain the U values for all groups between any primary input and the primary output s. The overall complexity of computing U values for all groups is O´mNµ, where N is gate count. For k captures per scan, we use a procedure similar to that in [19] to compute the switching probabilities. The procedure can be illustrated in Fig.…”

Section: A Path Delay Faults Testing For Scan-based Bistmentioning

confidence: 99%

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A testability metric for path delay faults and its application

Tsai

Cheng

Agrawal³

2000

Proceedings of the 2000 Conference on Asia South Pacific Design Automation - ASP-DAC '00

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Abstract-In this paper, we propose a new testability metric for path delay faults. The metric is computed efficiently using a non-enumerative algorithm. It has been validated through extensive experiments and the results indicate a strong correlation between the proposed metric and the path delay fault testability of the circuit. We further apply this metric to derive a path delay fault test application scheme for scan-based BIST. The selection of the test scheme is guided by the proposed metric. The experimental results illustrate that the derived test application scheme can achieve a higher path delay fault coverage in scan-based BIST. Because of the effectiveness and efficient computation of this metric, it can be used to derive other design-for-testability techniques for path delay faults.

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Section: A Path Delay Faults Testing For Scan-based Bistmentioning

confidence: 99%

Section: A Path Delay Faults Testing For Scan-based Bistmentioning

confidence: 99%

Section: A Path Delay Faults Testing For Scan-based Bistmentioning

confidence: 99%

Section: A Path Delay Faults Testing For Scan-based Bistmentioning

confidence: 99%

See 2 more Smart Citations

A testability metric for path delay faults and its application

Tsai

Cheng

Agrawal³

2000

Proceedings of the 2000 Conference on Asia South Pacific Design Automation - ASP-DAC '00

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“…Earlier works on built-in test generation for scan circuits using tests of the form (SI i ,T i ) were based on random patterns [9]- [11]. The methods of [9] and [10] do not achieve complete fault coverage, and all three methods do not guarantee that complete fault coverage would be achieved.…”

Section: Introductionmentioning

confidence: 99%

A partitioning and storage based built-in test pattern generation method for scan circuits

Pomeranz

Reddy

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conferen

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We describe a built-in test pattern generation method for scan circuits. The method is based on partitioning and storage of test sets. Under this method, a precomputed test set is partitioned into several sets containing values of different primary inputs or state variables. The on-chip test set is obtained by implementing the Cartesian product of the various sets. The sets are reduced as much as possible before they are stored on-chip in order to reduce the storage requirements and the test application time.

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Logic Testing

Wang¹,

Stroud²,

Cheng³

2009

Wiley Encyclopedia of Computer Science and Engineering

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Logic testing involves the process of testing the digital logic portion of a circuit under test (CUT). The digital logic can be reconfigured in test mode to include test logic to improve the testability and test quality of the circuit. Logic testing typically consists of applying a set of test stimuli to the inputs of the digital logic while analyzing the output responses. Depending on needs, both input test stimuli and output response analysis can be generated and performed inside the chip. Circuits that produce the correct output responses for all input stimuli pass the test and are considered to be fault free. Those circuits that fail to produce a correct response at any point during the test sequence are assumed to be faulty.

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Improving the test quality for scan-based BIST using a general test application scheme

Abstract: In

Cited by 19 publications

References 7 publications

A testability metric for path delay faults and its application

A testability metric for path delay faults and its application

A partitioning and storage based built-in test pattern generation method for scan circuits

Logic Testing

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