Impulse: building a smarter memory controller

Carter, J.; Hsieh, Wilson C.; Stoller, Leigh; Swanson, Mark R.; Zhang, Lixin; Brunvand, Erik; Davis, Al; Kuo, Ching-Hsiang; Kuramkote, R.; Parker, Michael; Schaelicke, Lambert; Tateyama, Terry

doi:10.1109/hpca.1999.744334

Cited by 157 publications

(119 citation statements)

References 19 publications

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“…Commands that are available in the command queue are processed by the command logic in FIFO order (5). A DRAM command is only dequeued when it is ready to appear on the DDRx command bus (6), and is issued to the DRAM subsystem at the next rising edge of the DRAM clock. …”

Section: Methodsmentioning

confidence: 99%

“…Impulse [6] is a memory controller that provides configurable access to memory blocks via physical address remapping to accelerate special functions (e.g., matrix transpose). Other proposals introduce programmability into controllers for on-chip SRAMs and DMA engines [1,2], or allow choosing among pre-defined QoS-aware scheduling algorithms for a DDRx memory controller [38].…”

Section: Intelligent Dram Controllersmentioning

confidence: 99%

“…A promising way of improving the versatility and efficiency of a memory controller is to make the controller programmable; indeed, programmability has proven useful in the context of other complex control tasks from DMA scheduling [1,2] to NAND Flash [3] and directory [4,5,6,7,8,9] control. In these and other architectural control problems, programmability allows the controller to be customized based on system requirements and performance objectives, makes it possible to perform in-field firmware updates to the controller, and enables application-specific control policies.…”

Section: Introductionmentioning

confidence: 99%

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PARDIS: A programmable memory controller for the DDRx interfacing standards

Bojnordi¹,

Ïpek²

2012

2012 39th Annual International Symposium on Computer Architecture (ISCA)

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Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource constraints on system performance. A promising way of improving the versatility and efficiency of these controllers is to make them programmable-a proven technique that has seen wide use in other control tasks ranging from DMA scheduling to NAND Flash and directory control. Unfortunately, the stringent latency and throughput requirements of modern DDRx devices have rendered such programmability largely impractical, confining DDRx controllers to fixed-function hardware.This paper presents the instruction set architecture (ISA) and hardware implementation of PARDIS, a programmable memory controller that can meet the performance requirements of a high-speed DDRx interface. The proposed controller is evaluated by mapping previously proposed DRAM scheduling, address mapping, refresh scheduling, and power management algorithms onto PARDIS. Simulation results show that the performance of PARDIS comes within 8% of an ASIC implementation of these techniques in every case; moreover, by enabling application-specific optimizations, PARDIS improves system performance by 6-17% and reduces DRAM energy by 9-22% over four existing memory controllers.

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Section: Methodsmentioning

confidence: 99%

Section: Intelligent Dram Controllersmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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PARDIS: A programmable memory controller for the DDRx interfacing standards

Bojnordi¹,

Ïpek²

2012

2012 39th Annual International Symposium on Computer Architecture (ISCA)

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“…[15] to lower memory latency by increasing row-buffer hits. The Impulse group at University of Utah [16] proposed adding an additional layer of address mapping in the memory controller to reduce memory latency by mapping non-adjacent data to the same cacheline and thus increasing cacheline sub-block usage.…”

Section: Related Workmentioning

confidence: 99%

Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling

Ganesh

Jaleel

Wang

et al. 2007

2007 IEEE 13th International Symposium on High Performance Computer Architecture

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“…This approach assumes uniform memory access time. The Impulse memory system by Carter et al [2] improves memory system performance by dynamically remapping physical addresses. This approach requires modifications to the applications and operating system.…”

Section: Related Workmentioning

confidence: 99%