In-design DFM CMP flow for block level simulation using 32nm CMP model

Ha, Naya; Lee, Jun Young; Paek, Seung‐Mann; Kim, Kee Sup; Chen, Kuang Han; Gower-Hall, Aaron; Gbondo-Tugbawa, Tamba; Hurat, Philippe

doi:10.1117/12.880899

Cited by 2 publications

(1 citation statement)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As a result, the need to create lithography and CMP-clean layouts during the design creation emerged, and requires a tighter integration of the lithography and CMP checks with design implementation tools. One of the challenges of DFM checks for IP such as the long-range CMP effects [1] is that the IP environment is often not known at the time of the design. Also, IP can be targeted to multiple designs, thus it becomes a key requirement that the lithography and CMP checks can be easily and accurately applied at block level.…”

Section: Introductionmentioning

confidence: 99%

<title>In-design hierarchical DFM closure for DFM-clean IP</title>

Tripathi¹,

Subramanian²,

Sharma³

et al. 2012

Design for Manufacturability Through Design-Process Integration VI

Self Cite

View full text Add to dashboard Cite

This paper presents the requirements for the Design for Manufacturability (DFM) checks such as lithography, and Chemical and Mechanical Polishing (CMP) at 28nm technology node, and the need to perform these DFM checks, early in the design phase and with minimum overhead. As a result, this reduces the risk of uncovering some DFM issues at the design tape out time when the changes in a design become expensive. Because IP blocks can be targeted to multiple designs, it is a key requirement that the lithography and CMP checks are accurate and designer-friendly and are easily applied at block-level. This paper describes the block-based methodology that allows the IP designers to perform quickly a comprehensive DFM analysis, including lithography and long-range CMP effects. This paper also explains the integration of the DFM checks into the design flow and correlation results between the block and chip-level checks.

show abstract

Section: Introductionmentioning

confidence: 99%