In-die mask registration for multi-patterning

Abstract

193nm immersion lithography is the mainstream production technology for the 20nm and 14nm logic nodes. Considering multi-patterning as the technology to solve the very low k1 situation in the resolution equation puts extreme pressure on the intra-field overlay, to which mask registration error is a major error contributor. The International Technology Roadmap for Semiconductors (ITRS) requests a registration error below 4 nm for each mask of a multi-patterning set forming one layer on the wafer. For mask metrology at the 20nm and 14nm logic nodes, maintaining a precision-to-tolerance (P/T) ratio below 0.25 will be very challenging. Mask registration error impacts intra-field wafer overlay directly and has a major impact on wafer yield. We will discuss a solution to support full in-die registration metrology on reticles.

Improving mask metrology for semiconductor manufacture

“…1 Measurements reveal that the actual mask quality with respect to registration depends on the number and the selection of mask measurement sites. 2 Figure 1 shows a mask with registration measured at 700 sites, including a variety of different device features. The 3 is 4.9nm, but different subsamples of 170 sites, both of which have reasonable mask coverage, produce quite different 3 values.…”