In-Line Defect Reduction From a Historical Perspective and Its Implications for Future Integrated Circuit Manufacturing

A Literature Review on Sampling Techniques in Semiconductor Manufacturing

“…For example, if the sampling plan is to control one lot every five lots, the objective is to limit the material at risk to not more than five. By always measuring the same lots or wafers, the technique enables the identification of the added defect density between sequential inspection steps [16]. Other advantages of a static sampling technique are the simplicity of implementation and adequate resourcing [14].…”

A Survey of Yield Modeling and Yield Enhancement Methods

“…In-line defect inspection tools detect defects by scattering a laser off the wafer surface and collecting the resulting image [111]. The tools detect physical deviations on product wafers by comparing the image at each position within a die with all adjacent die.…”

“…Specifically, during in-line scans a sample of defects is typically classified [111]. Defect classification has traditionally been done manually, and as a result, the fraction of classified defects has been small.…”

Test connections - tying application to process

“…CMP residue, Cu CMP pits, ECD pits, Cu hillocks, Cu CMP scratches, bridged trench pattern, blisters, blocked trench etch, ILD rip-outs are some examples of defects observed in early Cu/Low-K technology development. The opportunities for more defects increases as each technology generation continues to add more metal layers [4].…”

“…This has been enabled by tying together the structured test electrical failure diagnosis, the electrical net list, the physical net coordinate, and the physical in-line defect coordinate. The yield enhancement community is looking forward to this tool identifying yield sensitive issues unique to the random logic layout and circuit design practices [4].…”