In-place fabrication of nanowire electrode arrays for vertical nanoelectronics on Si substrates

Abstract

Vertical arrays of Pd nanowire electrodes with controllable and reproducible diameters and lengths are fabricated using a porous anodic alumina (PAA) template supported on a metallized Si substrate. The process described here employs a hydrogen plasma to penetrate the alumina pore barrier oxide prior to electrodeposition, enabling direct electrical contact with the back electrode metallization, thereby eliminating the need for electrochemical processing with high current or voltage pulsing that can lead to delamination or voiding. Electrical characteristics reveal Ohmic contact between the Pd nanowires and the underlying Ti conductive layer for samples with a range of pore diameters from 30to130nm. This process enables both the fabrication of vertical nanowire arrays on prefunctionalized substrates, as well as the in situ fabrication of contacts to semiconductor nanodevices using a thin-film nanowire array. The hydrogen plasma step is particularly well suited to the fabrication of carbon nanotube arrays in PAA by plasma-enhanced chemical vapor deposition.

Vertical Carbon Nanotube Devices With Nanoscale Lengths Controlled Without Lithography

“…The substantially lower conductance observed here is attributed to the series and contact resistances in the device. Perhaps, the main contribution is the thin alumina barrier at the bottom of each nanopore in the PAA template [6], which would create a large series resistance between the Pd nanowire and the underlying Ti layer. The low conductance of the semiconducting v-SWCNT is attributed to the normally OFF nature of semiconducting nanotubes in terms of band positions under no gate bias [illustrated in Fig.…”

“…The spacing between nanopores in the hexagonally arranged template is 100 nm, which yields a potential v-SWCNT density of 115 SWCNTs/µm 2 . Source contacts to the v-SWCNTs were made by electrochemically depositing Pd nanowires within the PAA pore bottoms, as described previously [6], [13]. The standard deviation in the length of these nanowires has been reported to be 4% [6] or less than 10 nm in the present case.…”

“…Source contacts to the v-SWCNTs were made by electrochemically depositing Pd nanowires within the PAA pore bottoms, as described previously [6], [13]. The standard deviation in the length of these nanowires has been reported to be 4% [6] or less than 10 nm in the present case. A spin-on glass (SOG) dielectric (Honeywell 214) was then applied at 6000 r/min for 30 s followed by a 450…”

“…These nanoporous templates can serve a variety of purposes from templating the synthesis of a nanomaterial [6], [7] to providing a support for in situ device fabrication [8]. The growth of SWCNTs from thin-film porous anodic alumina (PAA) templates has been recently achieved with a yield of not more than one SWCNT per pore [7], [9].…”

Toward surround gates on vertical single-walled carbon nanotube devices

“…Recently, templated synthesis, 10 backcontact formation, 11,12 and length control of v-SWCNTs supported in porous anodic alumina ͑PAA͒ have been reported. 13 Using these templates of v-SWCNTs, we present the fabrication of surrounding dielectrics and gates on nanotubes along with a facile means for controlling the device channel length.…”