In situ analysis of the stress development during fabrication processes of micro-assemblies

Abstract

Fabrication processes, like die attachment or plastic encapsulation, lead to thermal stresses in micro-assemblies due to CTE mismatches of the involved materials. In this paper, stress-and strain-sensitive test chips were used to measure in situ absolute stresses caused by die attach and encapsulation processes. Furthermore, deformations of assemblies over temperature were observed by white light interferometry and electronic speckle pattern interferometry.Applying these methods, e.g. the effect of entrapped air in thin adhesive layers of die attach assemblies on the absolute stresses in the silicon chip surface could be observed during cure. The resulting stress offset accounted up to 68 % of the thermal stresses at RT in the assembly. IntroductionAccording to common knowledge, die attach processes of silicon chips on substrates like copper lead frames or BGA interposers lead to high tensile stresses in the chip surface and to a warping of the assembly at room temperature (RT) due to CTE mismatches of the materials [1, 2]. Further on, stress states in the chip surfaces of BGA or PTO packages typically change to high compressive stresses at RT after encapsulation [3,4]. Consequently, stress-sensitive structures like semiconductor Hall-plates in magnetic sensors cause a signal offset or change of sensitivity of the sensors due to the pseudo-Hall effect [4]. The reliability of assemblies is also affected by stress induced phenomena like die cracking, die popping or fatigue cracking in plastic encapsulants [5,6].In this paper, an experimental approach was taken to analyze the influence of glass transition temperature, curing temperature, long term storage at RT, chemical and thermal shrinkage as well as non-linear material behavior of the die attach adhesive and the influence of moisture uptake of package materials on the stress developments in microassemblies.

Chip-side-healing as a basis for robust bare-chip assemblies

“…[4] For the analysis of chip fracture, besides knowledge of stress and strains, information about the breaking strength of the chips is also required. It will be shown, that this property is significantly influenced by the process of wafer dicing, as it leads to flaws and micro cracks in the chips.…”

“…Many investigations have been performed in order to find out to which kind and levels of stress chips are exposed in electronic components [4][5][6][7]. For instance, Fig.1 shows stress sensor chips prepared for in situ analysis during the die attachment process [4]. An overview of previous investigations revealed typical silicon die stresses in the range of ±50 MPa up to ±200 MPa [1][2][3][4][5][6][7].…”

“…For instance, Fig.1 shows stress sensor chips prepared for in situ analysis during the die attachment process [4]. An overview of previous investigations revealed typical silicon die stresses in the range of ±50 MPa up to ±200 MPa [1][2][3][4][5][6][7].…”

“…This means there are two ways to avoid chip fracture: stress reduction and increasing the chips breaking strength. Many investigations have been performed in order to find out to which kind and levels of stress chips are exposed in electronic components [4][5][6][7]. For instance, Fig.1 shows stress sensor chips prepared for in situ analysis during the die attachment process [4].…”

Investigation of modern electrically conductive adhesives for die-attachment in power electronics applications

“…Some of the coefficients of the used materials can be seen in Table 5. To measure the absolute stress and strain in the top layer of a silicon device, stress test chips are used [7]. The test chips were glued on three different substrates: DCB, copper and CGS.…”