In Situ Phosphorus-doped Polysilicon For Integrated Mems

Biebl, M.; Mulhern, Greg T.; Howe, Roger T.

doi:10.1109/sensor.1995.717138

Cited by 32 publications

(14 citation statements)

References 8 publications

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“…A low thermal-budget polysilicon suitable for post-CMOS integration strategies has been investigated at UC Berkeley [78]. By using a lower phosphine flow and a higher pressure than is used for MOS gate polysilicon and a deposition temperature of 585-590 C, an in situ doped and therefore low-resistivity polysilicon is deposited at a relatively rapid deposition rate.…”

Section: A Materials Properties 1) Residual Stressmentioning

confidence: 99%

“…By using a lower phosphine flow and a higher pressure than is used for MOS gate polysilicon and a deposition temperature of 585-590 C, an in situ doped and therefore low-resistivity polysilicon is deposited at a relatively rapid deposition rate. After rapid-thermal annealing (RTA) at 950 C, a low tensile residual stress with negligible gradient through the film thickness is produced [78]. This polysilicon material, followed by either RTA or furnace postdeposition anneals, has been used to fabricate flat cantilevers as long as 2 mm [79].…”

Section: A Materials Properties 1) Residual Stressmentioning

confidence: 99%

“…Long furnace anneals at higher temperatures have also been used to drive dopants into undoped polysilicon films sandwiched between phosphorus-rich oxide layers [20] with good stress-reduction results. Others customize the deposition process rather than rely completely on postdeposition annealing [78]. Device design (e.g., structural anchor placement and/or geometry, folded-suspension design, and location with respect to inertial mass) can also play an important role in mitigating the effects of as-deposited stress gradients [81].…”

Section: A Materials Properties 1) Residual Stressmentioning

confidence: 99%

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Surface micromachining for microelectromechanical systems

1998

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Section: A Materials Properties 1) Residual Stressmentioning

confidence: 99%

Section: A Materials Properties 1) Residual Stressmentioning

confidence: 99%

Section: A Materials Properties 1) Residual Stressmentioning

confidence: 99%

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Surface micromachining for microelectromechanical systems

1998

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“…As an alternative to these techniques, we propose to use in-situ phosphorus-doped polysilicon as a dopant source. Once deposited, the phosphorus can be transferred from the poly-Si to the silicon wafer by annealing, and the advantage of this technique is that it uses equipment readily available in a MEMS fab [1].…”

Section: Introductionmentioning

confidence: 99%

2d and 3d Doping of Silicon Mems Structures Using Phosphorus-Doped Polysilicon as a Dopant Source

Newby¹,

Zandi²,

Cute³

et al. 2018

2018 Solid-State, Actuators, and Microsystems Workshop Technical Digest

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We use in-situ phosphorus-doped LPCVD (low-pressure chemical vapour deposition) polysilicon as a dopant source for silicon wafers. We used this technique for "3D doping", where poly-Si is deposited over structures patterned in silicon-on-insulator (SOI) wafers, which enables higher doping levels, as diffusion is performed through three surfaces rather than one. This technique can also be used for doping of unpatterned wafers, and we have derived a relation which estimates the doping level achieved with 3D doping using only 4-point probe measurements on blanket wafers. The advantage of this doping method compared to standard methods is that it does not require dedicated equipment and can be carried out using tools commonly available in a MEMS fab.

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“…This focus directly results from constraints imposed by the MEMS processes. In many cases, the MEMS processes require high temperature steps [9,10,11] that exceed the maximum temperatures allowed for aluminum:silicon contacts[ 12, 131. Hybrid processes have followed several approaches. In many cases, the high temperature MEM steps are inserted into the IC process before the aluminum deposition steps-as is often done with integrated polysilicon micromachining [3,4,8].…”

Section: Introductionmentioning

confidence: 99%

Integrating SCREAM micromachined devices with integrated circuits

Shaw

MacDonald

Proceedings of Ninth International Workshop on Micro Electromechanical Systems

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We demonstrate the integration of SCREAM MEMS with a conventional, unmodified IC process. After fabricating the ICs, only two additional masks are needed to form the mechanical structure and the patterned metal interconnects. The mechanical structures are high-aspectratio beams formed from single-crystal silicon.SCREAM, which stands for Single-Crystal-silicon Reactive Etching and Metallization, is a low temperature process requiring conventional IC fabrication tools including the following: RIE, PVD, CVD and optical lithography. None of the processing steps expose the wafer to temperatures above 300°C. Also, the MEMS are independent of the substrate doping, and can be used with the substrate that is optimal for a particular IC process.We describe SCREAM as a "Portable" MEMS process. A portable process does not alter the ICs, can be run after the IC process, and does not require modification of commonly available IC processes.To support the claim that SCREAM is a portable process, we built structures on wafers containing industrially fabricated AD712 BiFET opamps. The ICs stayed within specification and the structures demonstrate successful fabrication adjacent to ICs.

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In Situ Phosphorus-doped Polysilicon For Integrated Mems

Cited by 32 publications

References 8 publications

Surface micromachining for microelectromechanical systems

Surface micromachining for microelectromechanical systems

2d and 3d Doping of Silicon Mems Structures Using Phosphorus-Doped Polysilicon as a Dopant Source

Integrating SCREAM micromachined devices with integrated circuits

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