In Situ XPS Chemical Analysis of MnSiO₃ Copper Diffusion Barrier Layer Formation and Simultaneous Fabrication of Metal Oxide Semiconductor Electrical Test MOS Structures

Abstract

Copper/SiO2/Si metal-oxide-semiconductor (MOS) devices both with and without a MnSiO3 barrier layer at the Cu/SiO2 interface have been fabricated in an ultrahigh vacuum X-ray photoelectron spectroscopy (XPS) system, which allows interface chemical characterization of the barrier formation process to be directly correlated with electrical testing of barrier layer effectiveness. Capacitance voltage (CV) analysis, before and after tube furnace anneals of the fabricated MOS structures showed that the presence of the MnSiO3 barrier layer significantly improved electric stability of the device structures. Evidence of improved adhesion of the deposited copper layer to the MnSiO3 surface compared to the clean SiO2 surface was apparent both from tape tests and while probing the samples during electrical testing. Secondary ion mass spectroscopy (SIMS) depth profiling measurements of the MOS test structures reveal distinct differences of copper diffusion into the SiO2 dielectric layers following the thermal anneal depending on the presence of the MnSiO3 barrier layer.

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“…Pre VPI, all spectra are dominated by an SiO 2 associated peak at approximately 533.3 eV. 64,65 A second peak at 532.1 eV, 532.0 eV and 531.7 eV in the P2VP, P4VP and PS spectra respectively is associated with C-O bonding as observed in the C 1s spectra in Figure 4, within the expected BE range. 57 Post VPI, accurately fitting the data results in the necessity of an additional, third component, located at 532.6 eV, 532.8 eV and 531.9 eV for the P2VP, P4VP and PS respectively.…”

Amorphous TaxMnyOz Layer as a Diffusion Barrier for Advanced Copper Interconnects

“…In Fig. 7a, the MOS capacitor sample without the barrier shows a negative flatband voltage shift (indicated by the green arrow) from −0.94 V to −2.54 V upon annealing owing to Cu + ion transport into the SiO 2 layer, which indicates a buildup of positive charge within the SiO 2 layer during annealing 18 . In addition, the hysteresis in the C–V curve indicates movement of the Cu + ion within the dielectric film during the C–V sweep.…”

“…It was noted that the flatband voltage of the MOS capacitor with the Ta x Mn y O z barrier before annealing was more negative than that of the as-deposited reference sample without the Ta x Mn y O z barrier (Cu/SiO 2 /Si). This can be attributed to intrinsic defects (positive charge was calculated as 4.63 × 10 −11 C) such as charges in SiO 2 or oxygen vacancies in the Ta x Mn y O z layer 18,41–43 . The flatband voltage moved to the positive region from −2.25 V to −0.49 V (indicated by the purple arrow) upon annealing owing to the removal of the intrinsic defects in the MOS capacitor sample and not from the diffusion of Cu + ions into the SiO 2 layer 18 .…”

“…This can be attributed to intrinsic defects (positive charge was calculated as 4.63 × 10 −11 C) such as charges in SiO 2 or oxygen vacancies in the Ta x Mn y O z layer 18,41–43 . The flatband voltage moved to the positive region from −2.25 V to −0.49 V (indicated by the purple arrow) upon annealing owing to the removal of the intrinsic defects in the MOS capacitor sample and not from the diffusion of Cu + ions into the SiO 2 layer 18 . In other words, there was no flatband voltage shift toward the negative region, and no hysteresis curve was observed in the MOS capacitor with the Ta x Mn y O z barrier, as shown in Fig.…”

“…10 The self-forming barrier was realized by spontaneously reacting the Cu– X alloying element with O and Si elements in the ILD material during post-metallization annealing 5 . Among the Cu– X alloying elements used 11–16 , an Mn alloying element 17,18 is widely used because the self-formed Mn oxide or Mn silicate has good reliability and is thinner than the dual Ta/TaN barrier. The thickness of the self-forming barrier is determined by the temperature of post-metallization annealing and the type of deposition method, such as PVD, chemical vapor deposition (CVD), or ALD 19–22 .…”