In 0.7 Ga 0.3 As channel n-MOSFETs (metal-oxide-semiconductor field-effect transistors) with Si-doped S/D and self-aligned NiInGaAs contact were demonstrated for the first time. The salicide-like metallization process employed a direct reaction between Ni and Si-doped InGaAs, followed by the removal of the unreacted Ni. As compared with n-MOSFETs with metallic Ni-InGaAs S/D (i.e. no Si doping in S/D), n-MOSFETs with Ni-InGaAs contact formed on Si-doped S/D show significantly improved OFFstate current I OFF in the linear and saturation regions.III-V materials such as Indium Gallium Arsenide (InGaAs) and Indium Arsenide (InAs) have significantly higher electron mobility than Silicon (Si) and are attractive for future high speed low power logic applications. 1-12 High performance III-V MOSFETs require low source and drain (S/D) series resistance R S/D , which includes metal-semiconductor contact resistance. 13-18 To achieve low R S/D in III-V FETs, S/D engineering such as selective growth of in situ doped S/D materials 19-21 and self-aligned contacts have been employed. [17][18]21,22 Metallic S/D is another attractive option 23-26 and should preferably be self-aligned to the gate stack. InGaAs channel n-MOSFETs with self-aligned metallic Ni-InGaAs S/D have been demonstrated recently. 25,26 However, the n-MOSFETs with metallic S/D suffer from high leakage current at metal/semiconductor junctions in S/D regions, leading to high drain to source and drain to body leakage current. Low drain junction leakage is needed to achieve low standby power consumption.In this work, In 0.7 Ga 0.3 As channel n-MOSFETs with Si-doped S/ D and self-aligned Ni-InGaAs contact were demonstrated for the first time. The spacer-less metallization process is similar to salicidation and drives the diffusion of Ni into InGaAs for reaction to form a conductive material. S/D implant (Si) and dopant activation anneal were performed before the metallization to form n-InGaAs/ p-InGaAs junction. The n-MOSFETs with Si-doped S/D and NiInGaAs contact show significantly suppressed off-state current I OFF as compared with n-MOSFETs with metallic Ni-InGaAs S/D.
Device FabricationThe fabrication process flow for In 0.7 Ga 0.3 As channel n-MOSFETs with self-aligned Ni-InGaAs contacts is summarized and illustrated in Fig. 1. 2-in. p-type (N A $1 Â 10 19 cm À3 ) InP wafer was used as starting substrates. A 500 nm thick In 0.53 Ga 0.47 As with p-type (Zn doped) doping concentration N A of 2 Â 10 17 cm À3 and a 20 nm thick In 0.7 Ga 0.3 As with N A of 2 Â 10 16 cm À3 were sequentially grown. After pregate cleaning using HCl and NH 4 OH solution, (NH 4 ) 2 S solution was used to passivate the In 03.7 Ga 0.3 As surface for suppression of surface oxidation. The sample was then quickly loaded into an atomic layer deposition (ALD) tool and $7 nm of Al 2 O 3 was deposited. TaN gate electrode (100 nm thick) was deposited by sputtering, patterned by optical lithography and etched by Cl 2 -based plasma.After gate stack formation, one batch of devices (implanted devices) w...