In-system jitter measurement using FPGA

Kubíček, Michal

doi:10.1109/radioelek.2010.5478560

Cited by 8 publications

(4 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Its total jitter was 35 ps at a clock frequency of 100 MHz. Based on these examples, we can conclude that the results obtained correlate with similar results in this scientific field [34]. Therefore, in addition to their main purposes, both MFs can be used to protect the 100 MHz clock TLs with acceptable jitter.…”

Section: Radiated Emissionssupporting

confidence: 78%

Serpentine and Spiral Routing Schemes for Microwave Transmission Lines to Ensure UWB Interference Immunity

Zhechev¹,

Belousov²,

Zabolotsky³

et al. 2022

Preprint

View full text Add to dashboard Cite

<p>This article analyzes novel, adventurous routing schemes employed in designing microwave transmission lines (TL). In contrast to traditional schemes, we propose to locate two independent traces close to each other. The strong electromagnetic coupling thus formed can cause unwanted crosstalk between traces. However, if their level is acceptable, we can use the suggested routing schemes to significantly increase the powerful interference immunity of the electrical circuits by using modal distortion. Two prototypes of such TLs in the form of a serpentine and a spiral were made in which the far-end crosstalk voltage waveforms do not exceed 4.4% of the useful signal amplitudes. We performed electrodynamic simulations and measurements of such TLs in a transverse electromagnetic cell in the frequency range from 10 MHz to 5.3 GHz. The investigated lines have a low level of radiated emissions. Experimental results show that the proposed TLs decrease the voltage amplitude of the ultra-wideband pulse by at least 4 times and the voltage change rate by 10.7 times and more. In addition, the effective voltage value on the load is decreased by at least 2.2 times. The spiral scheme was found to be better than the serpentine scheme in almost all parameters. Simultaneously, the electrodynamic approach is in full agreement with the experimental study.</p>

show abstract

Section: Radiated Emissionssupporting

confidence: 78%

Serpentine and Spiral Routing Schemes for Microwave Transmission Lines to Ensure UWB Interference Immunity

Zhechev¹,

Belousov²,

Zabolotsky³

et al. 2022

Preprint

View full text Add to dashboard Cite

show abstract

“…In terms of insertion loss from the eye diagrams, the signal amplitude decreased. In most applications, the demonstrated signal integrity level is typical [13][14][15][16]. Thus, for example, in microstrip transmission lines on dielectric with small tgδ, the jitter of 90 ps was obtained at the length that is many times less than the length of the investigated MF [17].…”

Section: Signal Integrity Analysismentioning

confidence: 99%

Signal integrity analysis for the four-layer reflection symmetric modal filter

Zhechev¹

2022

JRE

View full text Add to dashboard Cite

The article presents the results of signal integrity analysis for a four-layer reflection symmetric modal filter and determines a potential field of application for such devices. The authors performed a simulation and experimental study in the range from 0 to 1.5 GHz. The results show that the average level of insertion loss in the passband does not exceed -18 dB, which demonstrates good agreement. The insertion loss does not significantly attenuate the useful signal. After the modal filter was defined in the frequency domain, the authors used the Advanced Design System to analyze the time characteristics. Pseudorandom binary sequences with bitrates from 0.125 to 0.5 Gb/s were excited to the input of the device in the Advanced Design System. The eye diagrams show that the modal filter has an excellent performance in terms of signal integrity. Thus, at the fastest data rate, the jitter does not exceed 39.5 ps. The maximum value of amplitude noise was 71 mV. It is possible to achieve significantly lower values of jitter and amplitude noise for the modal filter using its optimal geometric and electrical parameters. The results of the electrodynamic simulation are in good agreement with the experimental results.

show abstract

“…Another technique is based on the measurement of the probability density function (PDF) of the edge distribution over one unit interval (UI) [8]. It utilizes two identical D-type flip-flops clocked by two separated clock signals, sampling the measured signal.…”

Section: Introductionmentioning

confidence: 99%

“…The presented jitter comparison technique combines the PDF of the edge distribution concept [8] with a tapped delay line (TDL) often used in TDC applications [7,9]. Some resource placement is manually chosen (in contrast to default automatic placement) to minimize the measurement errors between compared signals.…”

Section: Introductionmentioning

confidence: 99%

Relative Jitter Measurement Methodology and Comparison of Clocking Resources Jitter in Artix 7 FPGA

Wojciechowski,

Marcinek,

Pleskacz

2023

Electronics

View full text Add to dashboard Cite

Phase jitter is one of the crucial factors in modern digital electronics, determining the reliability of a design. This paper presents a novel approach to designing a jitter comparison system and methodology for FPGA chips using a Tapped Delay Line (TDL)—commonly used to implement a Time-to-Digital Converter (TDC). The design and its revision utilizing latches replacing some of the flip-flops are presented and discussed, with potential further improvements. A minimal temperature influence is verified and presented. The methodology of automated relative jitter measurements is discussed. Multiple different FPGA clock signal path configurations are measured, and the results are presented. The influence of clock routing is identified as critical when MMCM or PLL modules are omitted. It is demonstrated that with careful resource and routing allocation, the clock signal’s jitter performance does not have to be deteriorated by the absence of jitter filtering blocks. The proposed technique was implemented and verified and relative jitter performance was measured in the AMD/Xilinx Artix 7 35T FPGA platform.

show abstract

In-system jitter measurement using FPGA

Cited by 8 publications

References 3 publications

Serpentine and Spiral Routing Schemes for Microwave Transmission Lines to Ensure UWB Interference Immunity

Serpentine and Spiral Routing Schemes for Microwave Transmission Lines to Ensure UWB Interference Immunity

Signal integrity analysis for the four-layer reflection symmetric modal filter

Relative Jitter Measurement Methodology and Comparison of Clocking Resources Jitter in Artix 7 FPGA

Contact Info

Product

Resources

About