InAs/Si Hetero-Junction Channel to Enhance the Performance of DG-TFET with Graphene Nanoribbon: an Analytical Model

Dutta, Ritam; Subash, T.D.; Paitya, Nitai

doi:10.1007/s12633-020-00546-7

Cited by 12 publications

(4 citation statements)

References 21 publications

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“…This lacuna can be overcome using advance bandgap engineered heterojunction TFETs using nanowire structures. Intel demonstrated the superiority of heterojunction TFETs in [39] for low V DD operation with ON current of 1 μA μm −1 , OFF current of 200pA μm −1 and SS<60 mV/dec @ V DD = 0.3 V. In [40] a two-layer graphene InAs/Si hetero-TFET has achieved SS = 20.76 mV/decade and I I 10…”

Section: Tunnel Fetsmentioning

confidence: 99%

More-than-moore steep slope devices for higher frequency switching applications: a designer’s perspective

Chowdhury,

Sarkar,

Mahapatra

et al. 2024

Phys. Scr.

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The progress in IC miniaturization dictated by Moore’s Law has taken a leap from mere circuit integration to IoT enabled System-on-Chip (SoC) deployments. Such systems are connoted by contemporary advancements in the semiconductor industry roadmaps namely, ‘More-Moore’ and ‘More-than-Moore’ (MtM). For meaningful integration of digital and non-digital blocks, a power performance tradeoff is essential for maximum and fruitful utilization of the silicon area. Using the techniques under the MtM nomenclature allows the use of unconventional steep slope devices like Tunneling FETs, Negative Capacitance (NC) FETs, Gate-all-around FETs (GAA) and FinFETs etc., which can exhibit reasonable performance with lower supply voltages. Following the Device Technology Co-optimization (DTCO) and System Technology Co optimization (STCO) the advanced 3D heterogenous integration technologies allow sensors, analog/mixed signal and passive components to be assimilated within the same package as the CMOS blocks. Appropriate device engineering techniques like multi-gate architectures, vertical stacking transistors, compound semiconductors and alternate carrier transport phenomena are required to improve the current drive and scaling performance of advanced CMOS devices. CMOS based codesign is essential to realize new topologies for energy economical computation, sensing and information processing as the beyond CMOS steep slope devices are independently incapable of replacing conventional bulk CMOS devices. This article presents a detailed qualitative review of the various aspects of MtM beyond CMOS steep slope switches and their prospective integration technologies. For system level integration, various aspects of device performance and optimizations, related device-circuit interactions, dielectric technologies at the advance nanometer nodes have been probed into. Additionally, novel circuit topologies, synthesis algorithms and processor level performance evaluation using steep slope switches have been investigated. An exclusive compact overview for contemporary insights into integrated device-system development methodology and its performance evaluation is presented.

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Section: Tunnel Fetsmentioning

confidence: 99%

More-than-moore steep slope devices for higher frequency switching applications: a designer’s perspective

Chowdhury,

Sarkar,

Mahapatra

et al. 2024

Phys. Scr.

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“…The parameters A = 4 × 10 14 cm −3 •s −1 and B = 1.9 × 10 7 V•cm −1 in Kane's model are used. [38][39][40] However, it should be noted that the device would transit from a 3D electron system to a one-dimensional electron system with the scaling of the nanowire diameter. [41] In this case, the quantum confinement must be considered [42,43] and the modified Kane model for lower-dimensional systems should be used.…”

Section: Drawbacks Of the Qs Modelmentioning

confidence: 99%

A non-quasi-static model for nanowire gate-all-around tunneling field-effect transistors

Wang

et al. 2023

Chinese Phys. B

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The nanowire with gate-all-around (GAA) structure is widely considered as the most promising candidate for 3 nm technology with the best ability of suppressing the short channel effects and tunneling field effects transistors (TFETs) based on GAA structure also present improved performance. In this paper, a non-quasi-static (NQS) device model is developed for nanowire GAA TFETs. The model can predict the transient current and capacitance varied with operation frequency, which is beyond the ability of the already published quasi-static (QS) model. Excellent agreements between the model results and numerical simulations are obtained. Besides that, the NQS model is derived from the already proposed QS model including the current-voltage (I-V) and capacitance-voltage (C-V) characteristics. Therefore, the NQS model is compatible with the QS model for giving comprehensive understanding of GAA TFETs and would be helpful for the further study of TFET circuits based on nanowire GAA structure.

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“…In this section, the established device structure of an n-type double gate dual material P-i-N tunneling graphene nanoribbon field effect transistor (DG-DM-PiN-TGNFET) [21] is shown in Fig. 1.…”

Section: Device Structurementioning

confidence: 99%

Influence of Triple Material on Performance Study of Double Gate PiN Tunneling Graphene Nanoribbon FET for Low Power Logic Applications

Dutta¹,

Paitya²

2021

J. Nano- Electron. Phys.

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Influence of triple material having different work functions have been designed and investigated on a double gated P-i-N tunneling graphene nanoribbon field effect transistor (DG-TM-PiN-TGNFET) for improved device performance. A III/V compound material (InAs) has been used in the source region for this n-channel heterojunction tunnel FET, because of which stress -strain effect results better tunneling. Graphene, being a low band gap material, has been used as nano ribbon to tune suitably the energy bandgap as less as possible. In this paper, the three different materials are introduced to restrict the drain -source reverse tunneling and also improve the TFET device performance in terms of surface potential distribution, lateral -vertical electric field variation and transfer characteristics. This triple material-based DG-PiN-TGNFET structure provides better subthreshold swing of 18.56 mV/decade at 0.5 V supply voltage compared to single and double material based double gated TGN-FET structures. The entire simulation has been performed using two-dimensional mathematical TCAD device software. Moreover, the low threshold voltage encourages the proposed device best suitable for low power logic applications.

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InAs/Si Hetero-Junction Channel to Enhance the Performance of DG-TFET with Graphene Nanoribbon: an Analytical Model

Cited by 12 publications

References 21 publications

More-than-moore steep slope devices for higher frequency switching applications: a designer’s perspective

More-than-moore steep slope devices for higher frequency switching applications: a designer’s perspective

A non-quasi-static model for nanowire gate-all-around tunneling field-effect transistors

Influence of Triple Material on Performance Study of Double Gate PiN Tunneling Graphene Nanoribbon FET for Low Power Logic Applications

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