Incorporating Hot-Carrier Injection Effects Into Timing Analysis for Large Circuits

Fang, Jianxin; Sapatnekar, Sachin S.

doi:10.1109/tvlsi.2013.2296499

Cited by 16 publications

(8 citation statements)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Similar LUT-based approach does exist for other reliability issues, as the one used in [10] for calculating the degradation induced by hot-carrier injection (HCI). In the article, the authors describe a way to calculate the HCI-induced degradation by applying the following two formulae.…”

Section: Lut Approach For Hci Predictionmentioning

confidence: 99%

“…The HCI does not have a recovery phase as NBTI, and the degradation per se only happens during a signal transition. These two important degradation characteristics enabled the authors in [10] to accurately calculate the cumulative HCI-induced delay degradation analytically based on information provided by a two-dimensional LUT that is virtually equivalent to a conventional one.…”

Section: Lut Approach For Hci Predictionmentioning

confidence: 99%

“…Over a clock period, the transition time of a gate tends to occupy only a tiny portion of the period as all gates along the combinational path need to finish their transition in order to meet the timing constraint. The authors of [10] did not systematically examine the impact of their data binning method that approximates the transition probability calculation by reducing the number of transition time values to consider. In contrast, NBTI forces the pMOS to be biased over the entire clock period in the worst-case scenario.…”

Section: Lut Approach For Hci Predictionmentioning

confidence: 99%

“…Otherwise, the error grows unacceptable due to the non-linear relationship between probability and ∆V th . In short, the intrinsic nature of NBTI requires a different LUT approach from the one used in the article [10], and while the new approach could potentially also be used to predict HCI-induced degradation, it is not the case for the other way around.…”

Section: Lut Approach For Hci Predictionmentioning

confidence: 99%

See 3 more Smart Citations

Fast Estimation of NBTI-Induced Delay Degradation Based on Signal Probability

Bian

Shintani

Hiromoto

et al. 2016

IEICE Trans. Fundamentals

View full text Add to dashboard Cite

As technology further scales semiconductor devices, aging-induced device degradation has become one of the major threats to device reliability. Hence, taking aging-induced degradation into account during the design phase can greatly improve the reliability of the manufactured devices. However, accurately estimating the aging effect for extremely large circuits, like processors, is time-consuming. In this research, we focus on the negative bias temperature instability (NBTI) as the aginginduced degradation mechanism, and propose a fast and efficient way of estimating NBTI-induced delay degradation by utilizing static-timing analysis (STA) and simulation-based lookup table (LUT). We modeled each type of gates at different degradation levels, load capacitances and input slews. Using these gate-delay models, path delays of arbitrary circuits can be efficiently estimated. With a typical five-stage pipelined processor as the design target, by comparing the calculated delay from LUT with the reference delay calculated by a commercial circuit simulator, we achieved 4114 times speedup within 5.6% delay error.

show abstract

Section: Lut Approach For Hci Predictionmentioning

confidence: 99%

Section: Lut Approach For Hci Predictionmentioning

confidence: 99%

Section: Lut Approach For Hci Predictionmentioning

confidence: 99%

Section: Lut Approach For Hci Predictionmentioning

confidence: 99%

See 2 more Smart Citations

Fast Estimation of NBTI-Induced Delay Degradation Based on Signal Probability

Bian

Shintani

Hiromoto

et al. 2016

IEICE Trans. Fundamentals

View full text Add to dashboard Cite

show abstract

“…The objective of including a reliability improving circuit (RIC) in a CMOS architecture is to reduce variation in the system's figures of merit (FOM). Recent literature has addressed this issue for various radio frequency (RF), digital and digital-to-analog-conversion (DAC) circuits [5,[16][17][18][19][20][21][22][23][24][25][26][27][28][29]. For example, a reliability-sensitive power amplifier is presented in [5] which can be integrated with a wireless fidelity receiver to mitigate discharge/aging issues.…”

Section: Introductionmentioning

confidence: 99%

Common‐rail powered reliability improving technique for single‐supply complementary metal oxide semiconductor amplifiers

Roy¹,

Rashid²

2015

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

This paper presents a low-power technique to improve reliability of complementary metal oxide semiconductor (CMOS) amplifiers using a shared bias network for input gate and substrate of transistors. The circuit [named reliability improving circuit (RIC)] significantly reduces discrepancy in amplifier gain (S 21 , voltage gain), noise figure (NF/NF min) and output reflection-loss (ORL) parameters resulting from variation in threshold voltage, feature-width, device speed and supply rail. It performs well on both typical-(1.2 V) and low-voltage (0.7 V) platforms of a 90 nm CMOS technology and is able to maintain its consistency within a wide frequency coverage (10-30 GHz) for three different architectures (cascode, low-voltage cascode and common-source). This allows the RIC incorporated front-end to satisfy a broad range of gain, isolation, linearity and NF requirements. The scheme's biasing arrangement is powered from amplifier rails which permit the overall circuit to be driven from a single main supply. Analysis and simulation results demonstrate the technique improving consistency of figures of merit considerably against different aspects of process/system variation without significant degradation of radio frequency performance.

show abstract