Incorporation of hard-fault-coverage in model-based testing of mixed-signal ICs (poster paper)

Abstract

The application of the Linear Error Mechanism Modeling Algorithm (LEMMA [1]) to various DAC and ADC architectures has raised the issue of including hard-fault-coverage as an integral part of the algorithm.In this work, we combine defect-oriented functionality tests and specification-oriented linearity tests of a Mixed-Signal IC to save test time. The key development is a novel test point selection strategy which not only optimizes the INL-prediction variance of the model, but also satisfies hardfault-coverage constraints.Introduction Using well-established system identification methods to cut the costs of testing mixed-signal ICs has recently attracted much research effort [2,3]. The ultimate aim is to automate the development of test procedures and to ensure an optimal trade-off between test time per part and the confidence of the test result. A paradigm, called the Linear Error Mechanism Modeling Algorithm has been developed and a tutorial introduction of this algorithmic approach is given in [1].Strategies to develop linear models for parametric-faults, such as the integral nonlinearity (INL) of a DAC or ADC, caused by spreads in on-chip component values have been independently implemented in two software packages [4,5]. Both implementations select test points by unconstrained minimization of the prediction variance of the linear model. The 12-bit DAC we consider is targeted at low-cost controlloop applications where the time spent on testing this part is critical.Traditionally, functionality tests are performed before verifying that the specifications of the analog part of the circuit are met. In [6] it has been pointed out that both aspects of "faulty devices: excessive process deviations and spot defects... must be accounted for when developing and evaluating general test methodologies." We go even further, by suggesting to interweave functionality and linearity tests in order to save test time, which adds value to our model-based test methodology, called LEMMA. During the poster presentation this will be demonstrated in detail for our 12-bit example DAC, where hard-fault-coverage is embedded in the linearity test by means of a novel test point selection strategy.The set of hard-faults we consider here has the property that any fault becomes apparent in the full-factorial measurement, i.e. for every fault, there exists at least one code £ such