Increase in Oxide Trap Density Due to the Implementation of High-k and Al₂O₃ Cap Layers in Thick-Oxide Input-Output Transistors for DRAM Applications

Abstract

The impact of the implementation of a high-k/metal-gate (HKMG) stack on the oxide integrity of input-output (I/O) pMOSFETs for DRAM periphery applications is investigated by means of low-frequency (LF) noise spectroscopy. It is shown that the predominant 1/f noise is governed by number fluctuations, irrespective of the details of the gate stack. However, the trap density in the 5 nm SiO2 gate oxide, derived from the noise power spectral density is significantly increased by the application of the HKMG and/or Al2O3 cap and the subsequent diffusion anneal at 900 oC.