2005
DOI: 10.31399/asm.cp.istfa2005p0206
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Increasing Planarity for Failure Analysis Using Blocked Reactive Ion Etching Combined with Planar Polish

Abstract: Challenges in sample preparation for semiconductor failure analysis are always increasing as more complex material and smaller dimensions are required to meet the needs of the semiconductor industry. These changes require the constant need for more refined procedures in all areas of sample preparation, including mechanical polish. This paper presents a newly modified technique which increases the planarity at the critical edge of the sample and results in a larger planar region of interest. The novel method co… Show more

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“…To perform PFA on the failed ET, we tried to polish the sample to V4 and identify the physical defect that resulted in the high resistance. The area to be inspected is as big as > 50000 μm 2 where a single metal line "snake" runs through the whole ET structure in the wafer scribe line. PVC inspection in SEM is needed to locate the defect position which requires intact connection in the metal line without any damage such as metal bridging or metal broken from the sample preparation.…”
Section: Case 3: Using Controlled Slurry Polishing Combined Withmentioning
confidence: 99%
See 1 more Smart Citation
“…To perform PFA on the failed ET, we tried to polish the sample to V4 and identify the physical defect that resulted in the high resistance. The area to be inspected is as big as > 50000 μm 2 where a single metal line "snake" runs through the whole ET structure in the wafer scribe line. PVC inspection in SEM is needed to locate the defect position which requires intact connection in the metal line without any damage such as metal bridging or metal broken from the sample preparation.…”
Section: Case 3: Using Controlled Slurry Polishing Combined Withmentioning
confidence: 99%
“…However, if the sample comes with the accidental damage or the naturally generated edge rounding during the delayering, the problems have to be fixed to restore the sample to the former condition before the polishing is continued to the target layer. The common problems encountered in the delayering include sample cracks, polishing scratches, and surface unevenness [2][3][4][5][6]. The sample cracks refer to the sample die breaking into pieces due to chipping, dropping or crushing, which would pose great challenges to the following polishing if the crack lines extend ASTESJ ISSN: 2415-6698 across the defect area.…”
Section: Introductionmentioning
confidence: 99%