Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks

Cuesta, B.; Ros, Alberto; Gómez, María E.; Robles, Antonio; Duato, J.

doi:10.1145/2000064.2000076

Cited by 115 publications

(159 citation statements)

References 19 publications

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“…While previous proposals classified memory accesses for guiding data placement [7], [13] or optimizing coherence protocols (e.g., reducing self-invalidation [2], reducing directory pressure [11], [21]), SPEL relies on the delineation of xDRF regions to minimize the coherence maintenance while providing SC guarantees, for any code. Next we review the most widely adopted approaches for memory access classification.…”

Section: B Classification Of Memory Accessesmentioning

confidence: 99%

“…OSbased classification) [7], [10], [11] classifies a memory access as private if the entire accessed page is referenced only by one thread, during the entire execution. Hence, in practice, the majority of memory accesses are finally classified as shared.…”

Section: ) Os-based Classificationmentioning

confidence: 99%

“…Examples of run-time classifications are OS-based [7], [10], [11] (Section II-B1), TLB-based [32], or hardware-based [9], [12], [15], [33] methods. TLB-based methods are able to capture more private pages, but at the cost of extra traffic and complexity.…”

Section: Related Workmentioning

confidence: 99%

“…To exploit this opportunity, numerous proposals revolve around identifying the nature of memory accesses as private or shared [7], [8], [9], [10], [11], [12], [13], [14], [15] for optimizing the coherence protocol or, for example, enhancing data placement. While these optimized coherence protocols outperform traditional protocols, the underlying techniques for classifying accesses still lack accuracy (Section II), due to the classification of memory accesses based on the private or shared nature of the target data.…”

Section: Introductionmentioning

confidence: 99%

“…While these optimized coherence protocols outperform traditional protocols, the underlying techniques for classifying accesses still lack accuracy (Section II), due to the classification of memory accesses based on the private or shared nature of the target data. Performed at runtime, such a classification is either coarse-grained [7], [10], [11] or increases hardware complexity [9], [12], [15]. Performed at compile-time, it must remain conservative, due to memory accesses which cannot be fully disambiguated statically [8], [13].…”

Section: Introductionmentioning

confidence: 99%

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A Dual-Consistency Cache Coherence Protocol

Ros

Jimborean

2015

2015 IEEE International Parallel and Distributed Processing Symposium

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Abstract-Weak memory consistency models can maximize system performance by enabling hardware and compiler optimizations, but increase programming complexity since they do not match programmers' intuition. The design of an efficient system with an intuitive memory model is an open challenge. This paper proposes SPEL, a dual-consistency cache coherence protocol which simultaneously guarantees the strongest memory consistency model provided by the hardware and yields improvements in both performance and energy consumption. The design of the protocol exploits a compile-time identification of code regions which can be executed under a less restrictive, thus optimized protocol, without harming correctness. Outside these regions, code is executed under a more restrictive protocol which enforces sequential consistency. Compared to a standard directory protocol, we show improvements in performance of 24% and reductions in energy consumption of 32%, on average, for a 64-core chip multiprocessor.

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Section: B Classification Of Memory Accessesmentioning

confidence: 99%

Section: ) Os-based Classificationmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Dual-Consistency Cache Coherence Protocol

Ros

Jimborean

2015

2015 IEEE International Parallel and Distributed Processing Symposium

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2013

Time‐Predictable Architectures

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Fine‐grain data management directory for OpenMP 4.0 and OpenACC

Jaeger

Carribault

Pérache

2014

Concurrency and Computation

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SUMMARYToday's trend to use accelerators in heterogeneous systems forces a paradigm shift in programming models. The use of low-level APIs for accelerator programming is tedious and not intuitive for casual programmers. To tackle this problem, recent approaches focused on high-level directive-based models, with a standardization effort made with OpenACC and the directives for accelerator in the latest OpenMP 4.0 release. The pragmas for data management automatically handle data exchange between the host and the device. To keep the runtime simple and efficient, severe restrictions hinder the use of these pragmas. To address this issue, we propose the design for a directory, along with a reduced runtime application binary interface, to handle correctly data management in these standards. A few improvements to our directory allow a more flexible use of data management pragmas, with negligible overhead. Our design fits a multi-accelerator system.

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Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks

Cited by 115 publications

References 19 publications

A Dual-Consistency Cache Coherence Protocol

A Dual-Consistency Cache Coherence Protocol

Bibliography

Fine‐grain data management directory for OpenMP 4.0 and OpenACC

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