Increasing the power efficiency of application specific instruction set processors using datapath optimization

Glokler, T.; Bitterlich, S.; Meyr, H.

doi:10.1109/sips.2000.886754

Cited by 6 publications

(2 citation statements)

References 2 publications

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“…Other techniques such as instruction set optimization [11,12,13], memory access reduction [14,15] and low complexity algorithms [16,17] are also proposed to reduce the dynamic power dissipation in both logics and memories. However, in this paper we will focus mainly on low-power circuit techniques.…”

Section: Dynamic Power Reduction Techniquesmentioning

confidence: 99%

Technology Scaling And Low Power Design Techniques

Rani¹,

Rao²

2012

CVRJST

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Scaling the feature size of transistor made a remarkable advancement in silicon industry. The demand for power-sensitive design has grown significantly in recent years due to growth in portable applications. The need for power-efficient design techniques is increasing. Various efficient design techniques have been proposed to reduce both dynamic as well as static power in state-of-the-art VLSI applications. In this paper, different circuit design techniques both static and dynamic are discussed that reduce the power consumption.

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Section: Dynamic Power Reduction Techniquesmentioning

confidence: 99%

Technology Scaling And Low Power Design Techniques

Rani¹,

Rao²

2012

CVRJST

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“…This can be done either by designing a fully dedicated circuit, or by combining a programmable core with application specific co-processors. Indeed, it has been shown that for many computeintensive applications, the use of specialized co-processors could dramatically improve the power efficiency of a design (up to more than one order of magnitude [3]). …”

Section: Introductionmentioning

confidence: 99%

Ultra low-power FSM for control oriented applications

Pasha

Derrien

Sentieys

2009

2009 IEEE International Symposium on Circuits and Systems

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In this paper, we propose an approach combining the use of distributed hardware tasks implemented as Finite State Machines (FSM) and power gating techniques to obtain ultra low-power implementations. We target for control dominated applications represented as control task graphs, and propose a complete flow including a C to hardware task compiler. Our approach is validated experimentally and shows impressive improvement over software implementation on leading edge low-power microcontrollers such as the MSP430.978-1-4244-3828-0/09/$25.00 ©2009 IEEE

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