Increasing the security level of analog IPs by using a dedicated vulnerability analysis methodology

Beringuier-Boher, Noemie; Hély, David; Beroulle, Vincent; Damiens, Joël; Candelier, P.

doi:10.1109/isqed.2013.6523662

Cited by 8 publications

(3 citation statements)

References 19 publications

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“…For instance, Boher et al proposed modifying the current IC design process, as shown in Fig. 22 (a), and exposing all existing vulnerabilities during the AMS-IP design process to identify potential security risks [123], as shown in Fig. 22 (b).…”

Section: ) Chip Verification Layermentioning

confidence: 99%

“…Block diagram of IC design flow. (a) Current IC design flow without vulnerabilities analysis[123]. (b) AMS-IP based design flow with vulnerabilities analysis[123].…”

mentioning

confidence: 99%

“…(a) Current IC design flow without vulnerabilities analysis[123]. (b) AMS-IP based design flow with vulnerabilities analysis[123]. (c) Security IP based design flow with vulnerabilities analysis[124].…”

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confidence: 99%

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A Survey on Machine Learning Against Hardware Trojan Attacks: Recent Advances and Challenges

et al. 2020

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The remarkable success of machine learning (ML) in a variety of research domains has inspired academic and industrial communities to explore its potential to address hardware Trojan (HT) attacks. While numerous works have been published over the past decade, few survey papers, to the best of our knowledge, have systematically reviewed the achievements and analyzed the remaining challenges in this area. To fill this gap, this article surveys ML-based approaches against HT attacks available in the literature. In particular, we first provide a classification of all possible HT attacks and then review recent developments from four perspectives, i.e., HT detection, design-for-security (DFS), bus security, and secure architecture. Based on the review, we further discuss the lessons learned in and challenges arising from previous studies. Despite current work focusing more on chip-layer HT problems, it is notable that novel HT threats are constantly emerging and have evolved beyond chips and to the component, device, and even behavior layers, therein compromising the security and trustworthiness of the overall hardware ecosystem. Therefore, we divide the HT threats into four layers and propose a hardware Trojan defense (HTD) reference model from the perspective of the overall hardware ecosystem, therein categorizing the security threats and requirements in each layer to provide a guideline for future research in this direction.

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Section: ) Chip Verification Layermentioning

confidence: 99%

“…Block diagram of IC design flow. (a) Current IC design flow without vulnerabilities analysis[123]. (b) AMS-IP based design flow with vulnerabilities analysis[123].…”

mentioning

confidence: 99%