Increasing the Transistor Count by Constructing A Two-Layer Crystal Square on A Single Chip

El-Aawar, Haissam

doi:10.5121/ijcsit.2015.7308

Cited by 9 publications

(5 citation statements)

References 6 publications

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“…The widespread use of binary logic was due to their simple realization by available relays, vacuum tube, diodes, and final transistors [6]. The new microprocessor fabrication needs about 10 9 transistors while the number of connections is approximately 10 11 [7]. The engineering viewpoint can easily lead to the number of connections is 100 more than the number of transistors.…”

Section: Motivationmentioning

confidence: 99%

“…The transistor schematic diagram for Eq. (7) From the disadvantages of truncated difference operator, when the two inputs for this operator be large and equal, for example 15 µA, the output will not be 0. Therefore, to improve the performance of this circuit, one switch operator and two truncated difference operator have been added to the design.…”

Section: Figure 11mentioning

confidence: 99%

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Design and Implementation 4-Bit Quaternary MVL Arithmetic and Logic Unit

2018

Teh. vjesn.

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In the recent years, there were major importance to Multiple Valued Logic (MVL), where the most common reasons for considering the implementation of MVL circuits better then binary valued circuits are that reducing wiring congestion as compared to binary circuits, using a single conductor to transmit three or more discrete voltage or current values allows for greater information content per wire and the circuit cost models would be more economical. Therefore, in this paper the MVL concepts have been used to design 4-bit quaternary MVL Arithmetic and Logic Unit, which is considered a basic unit of a MVL microprocessor. It is the "heart" of a microprocessor and we could say that everything else in the microprocessor is there to support the ALU. The proposed Arithmetic and Logic Unit will do the operations as Addition, Subtraction, Maximum, Minimum and Invert. Simulation Program with Integrated Circuit Emphasis (SPICE) tool in Cadence simulator used in simulation the proposed Arithmetic and Logic Unit. The simulation results tells that the design is more efficient compared with the binary ALU and the circuit will be less area and less number of transistors.

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Section: Motivationmentioning

confidence: 99%

Section: Figure 11mentioning

confidence: 99%

Design and Implementation 4-Bit Quaternary MVL Arithmetic and Logic Unit

2018

Teh. vjesn.

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“…A computer is one of the technologies that got improved. The number of transistors with each new CPU generation increased without rapidly changing the die size [1]. Such advancements allow some computers to compute much more complex problems on different sizes of machines.…”

Section: Introductionmentioning

confidence: 99%

Optimizing Hand Gesture Recognition Using CNN Model Supported by Raspberry pi for Self-Service Technology

Rangkuti

Athalaa

Indallah

et al. 2023

JOIV : Int. J. Inform. Visualization

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This study describes the optimization of hand gesture recognition on Raspberry Pi 4 technology has advanced over the past years, some computers are now able to compute much more complex problems like real-time object detection. But for small devices, optimization is required to run in real-time with acceptable performance in terms of latency and low-cost effect on accuracy. Low latency is a requirement for most technology, especially when integrating real-time object detection as input into Self-Service Technology on Raspberry Pi for the store. This research was conducted on 288 pictures with six types of chosen hand gestures for command inputs that have been configured in the Self-Service Technology as a training dataset. In the experiment carried out with 5 CNN object detection models were used, namely YOLOv3-Tiny-PRN, YOLOv4-Tiny, MobileNetV2-Yolov3-NANO, YOLO-Fastest-1.1, and YOLO-Fastest-1.1-XL. Based on the experiment after optimization, the FPS and inference time metrics have improved performance. The performance improves due to a gained average value of FPS by 3 FPS and a reduced average value of inference time by 119,260 ms. But such an improvement also comes with a reduction in overall accuracy. The rest of the parameters have a reduced score on Precision, Recall, F1-Score, and some for IoU. Only YOLO-Fastest-1.1-XL have an improved value of IoU by about 0.58%. Some improvements in the CNN and dataset might improve the performance even more without sacrificing too much on the accuracy, but it's most likely suitable for another research as a continuation of this topic.

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“…Packing more functionality, with a reduction in cost, are two of the key challenges for system designers. According to Moore's law, the size of transistors in a dense integrated circuit has decreased exponentially (El-Aawar, 2015), which means that manufacturers need to unswervingly deposit very small paste volumes at the correct positions. Problems encountered during the printing process are insufficient solder paste, torn prints, bridging or short circuiting and pad oxidation.…”

Section: Introductionmentioning

confidence: 99%

Defect minimization and process improvement in SMT lead-free solder paste printing: a comparative study

Asghar

Rehman

Aman

et al. 2019

SSMT

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Purpose The purpose of this paper is to investigate and minimize the printing-related defects in the surface mount assembly (SMA) process. Design/methodology/approach This paper uses an experimental approach to explore process parameter and printing defects during the SMA process. Increasing printing performance, various practices of solder paste (Ag3.0/Cu0.5/Sn) storage and handling are suggested. Lopsided paste problem is studied by varying squeegee pressure and the results are presented. Unfilled pads problems are observed for ball grid array (BGA) and quad flat package (QFP) which is mitigated by proper force tuning. In this paper, a comparative study is conducted which evaluates the manifestation of printing offset due to low-grade stencil. The input/output (I/O) boards were oxidized when the relative humidity was maintained beyond 70 per cent for more than 8 h. This pad oxidation problem is overcome by proper printed circuit board (PCB) handling procedures. When the unoptimized line is used, the paste wedged in the stencil and influences the performance of the screen printer, for this reason, an optimized line is proposed that minimize the printing defects. Findings The key findings are as follows: in the SMA process, printing quality is directly associated with solder paste quality. Experimentally, it is observed that a considerable variance in solder deposition occurred when the front and rear squeegee have different configurations. High-grade and unsoiled stencil results in superior paste deposition and less distinction. Insufficient solder paste and bridge problems also occur in printing when PCB pads are oxidized. Optimized line resolves solder paste clog issues, associated with stencil’s aperture. The cooling arrangement on the conveyor, after reflow, explicates hot jig problem. Control environmental conditions minimized static charges and printing defects. Originality/value The preceding studies emphasis mostly on the squeegee pressure, while other important parameters are not completely investigated. Moreover, it is very imperative to concurrently measure all parameters while varying the environmental conditions. This study highlights and provides an experimental approach to various PCB printing defects, and a comparative study has been conducted that concurrently measure all process parameters.

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Increasing the Transistor Count by Constructing A Two-Layer Crystal Square on A Single Chip

Abstract: ABSTRACT

Cited by 9 publications

References 6 publications

Design and Implementation 4-Bit Quaternary MVL Arithmetic and Logic Unit

Design and Implementation 4-Bit Quaternary MVL Arithmetic and Logic Unit

Optimizing Hand Gesture Recognition Using CNN Model Supported by Raspberry pi for Self-Service Technology

Defect minimization and process improvement in SMT lead-free solder paste printing: a comparative study

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