Incremental compilation for logic emulation

Tessier, Russell

doi:10.1109/iwrsp.1999.779059

Cited by 5 publications

(4 citation statements)

References 10 publications

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“…Figure 1 multi-FPGA systems using the mesh style have been reported in [3,10,7,15,17,20]. The original Quickturn emulation system [21] and the IKOS system [8] are examples of commercial multi-FPGA systems that utilize this architecture [19].…”

Section: Figure 1: Two Main Interconnection Architecturesmentioning

confidence: 99%

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Incremental reconfiguration of multi-FPGA systems

Lee

Wong

2002

Proceedings of the 2002 ACM/SIGDA Tenth International Symposium on Field-Programmable Gate Arrays

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In reconfigurable computing, circuits implemented on multi-FPGA systems have to be incrementally modified. Since reconfiguring an FPGA is time-consuming, the time for reconfiguration depends on the number of FPGAs to be reconfigured. Our objective is to reduce the number of such FPGAs. In this paper, we consider the specific problem of incrementally reconfiguring a multi-FPGA system that utilizes the direct interconnection architecture, where routing connections between FPGAs are to neighbors that are near. This problem can be divided into a net addition problem and a net deletion problem. We show that the net addition problem is a generalization of the NP-complete Steiner tree problem. Our algorithm for this problem is based on an adaptation of the Klein-Ravi approximation algorithm for the node-weighted Steiner tree problem. As for the net deletion problem, we prove that it is NP-complete but the problem is solvable in polynomial time for tree topologies. Based on the algorithm for trees, we design an effective heuristic algorithm for the general net deletion problem. Finally, we present an algorithm for solving the incremental reconfiguration problem which handles both placement of new gates and inter-FPGA routing.

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Section: Figure 1: Two Main Interconnection Architecturesmentioning

confidence: 99%

“…Tessier in [19] dealt with the problem of incremental compilation in logic emulation. Their solution involves using a multi-way partitioning algorithm to incrementally partition the circuit to minimize the interconnections of the new circuit.…”

Section: Related Researchmentioning

confidence: 99%

Incremental reconfiguration of multi-FPGA systems

Lee

Wong

2002

Proceedings of the 2002 ACM/SIGDA Tenth International Symposium on Field-Programmable Gate Arrays

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“…Generally, schedule modifications are localized to a small part of the overall schedule, which make the algorithms difficult to apply to parallel verification. In an earlier version of the work presented in this paper, Tessier presents a greedy incremental scheduler for logic emulation [20]. Perhaps the most relevant incremental scheduling work has been performed in regards to land-based data transmission networks.…”

Section: Incremental Compilation Software Flowmentioning

confidence: 99%

Incremental compilation for parallel logic verification systems

Tessier

Jana

2002

IEEE Trans. VLSI Syst.

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Although simulation remains an important part of application-specific integrated circuit (ASIC) validation, hardware-assisted parallel verification is becoming a larger part of the overall ASIC verification flow. In this paper, we describe and analyze a set of incremental compilation steps that can be directly applied to a range of parallel logic verification hardware, including logic emulators. Important aspects of this work include the formulation and analysis of two incremental design mapping steps: the partitioning of newly added design logic onto multiple logic processors and the communication scheduling of newly added design signals between logic processors. To validate our incremental compilation techniques, the developed mapping heuristics have been integrated into the compilation flow for a field-programmable gate-array-based Ikos VirtuaLogic emulator [1]. The modified compiler has been applied to five large benchmark circuits that have been synthesized from register-transfer level and mapped to the emulator. It is shown that our incremental approach reduces verification compile time for modified designs by up to a factor of five versus complete design recompilation for benchmarks of over 100 000 gates. In most cases, verification run-time following incremental compilation of a modified design matches the performance achieved with complete design recompilation.

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“…Different approaches have been reported in order to reduce the development time [4] [5]. The goal of this work is the use of the standard VHDL language in order to simulate the parts of a circuit we want to redesign, while emulating the rest of the circuit without having to repeat the logic synthesis and technology mapping steps in each iteration.…”

Section: Introductionmentioning

confidence: 99%

Speeding up hardware prototyping by incremental simulation/emulation

Cañellas

Moreno²

Proceedings 11th International Workshop on Rapid System Prototyping. RSP 2000. Shortening the Path From Specification to Protot

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In this paper we describe a method for the automatic construction of a testbench, able to dynamically communicate a standard VHDL simulator with a logic emulator by means of text files. The proposed approach significantly reduces turn-around times in an emulation based rapid system prototyping environment. In this way, time consuming logic synthesis and technology mapping steps are moved, in the design cycle, after a previous functional verification.

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Incremental compilation for logic emulation

Cited by 5 publications

References 10 publications

Incremental reconfiguration of multi-FPGA systems

Incremental reconfiguration of multi-FPGA systems

Incremental compilation for parallel logic verification systems

Speeding up hardware prototyping by incremental simulation/emulation

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