Incremental gate sizing for late process changes

Abstract

We present a new framework to measure ECO cost resulting from process changes late in the design cycle and perform incremental gate sizing to minimize this layout and timing verification cost. Compared to a commercial solver, ECO costs are reduced up to 99% in changed area, and up to 96% in non-critical changed pins.

ECO cost measurement and incremental gate sizing for late process changes

“…These changes are derived from a two year change in a commercial 45nm process as in [Lee and Gupta 2010], and they create a negative-slack timing violation that is repaired using the algorithm LPECO-S. For comparison, the algorithm is run without the ECO costs (LP No Eco Cost), and the commercial design tool is also used to repair the timing violation in the post-route incremental mode with the optimization effort set to high. The commercial tool has the ability to add buffers, on top of sizing gates, and while this provides an advantage over LPECO-S, we show that LPECO-S still performs better.…”

“…the y ik may be greater than 0, but less than 1, the gates are assigned using the same indeterminate assignment algorithm as in [Lee and Gupta 2010]. In this method, alternate cell options are considered that can provide the same slack improvement with less power and ECO cost.…”

“…In contrast to [Chinnery and Keutzer 2005], to account for the downstream delays due to slew effects, the negative change in the slack is used as δ ik in place of the actual delay change. Also, in contrast to [Lee and Gupta 2010], the restriction preventing neighboring gates to change is dropped.…”

“…Incorporating the ECO cost into the Linear Programming gate sizing framework in [Chinnery and Keutzer 2005] results in: We denote this algorithm LPECO-S, a simplified version of the LPECO from [Lee and Gupta 2010], that minimizes a weighted objective of power and ECO cost. The variables t i , d i0 and δ ik are related to the timing of the design, and they propagate the arrival times down the graph to enforce setup time constraints.…”

“…The resulting model is fed into an optimization loop which minimizes the ECO cost and power while meeting the timing constraints. In comparison to the prior work in [Lee and Gupta 2010], an improved ECO area metric and a simplified version of the algorithm is presented in this paper, which has improved performance, and faster runtimes.…”