Incremental hardware estimation during hardware/software functional partitioning

Vahid, Frank; Gajski, Daniel D.

doi:10.1109/92.407006

Cited by 54 publications

(27 citation statements)

References 14 publications

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“…One important limitation of this work is a simple additive HW area estimation model that does not consider resource sharing-this could potentially be overcome in a future implementation with an approach like [8].…”

Section: Resultsmentioning

confidence: 99%

Efficient search space exploration for HW-SW partitioning

Banerjee

Dutt

2004

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES+ISSS

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Hardware/software (HW-SW) partitioning is a key problem in the codesign of embedded systems, studied extensively in the past. One major open challenge for traditional partitioning approaches -as we move to more complex and heterogeneous SOCs -is the lack of efficient exploration of the large space of possible HW/SW configurations, coupled with the inability to efficiently scale up with larger problem sizes. In this paper, we make two contributions for HW-SW partitioning of applications represented as procedural callgraphs: 1) we prove that during partitioning, the execution time metric for moving a vertex needs to be updated only for the immediate neighbours of the vertex, rather than for all ancestors along paths to the root vertex; consequently, we observe faster run-times for move-based partitioning algorithms such as Simulated Annealing (SA), allowing call graphs with thousands of vertices to be processed in less than a second, and 2) we devise a new cost function for SA that allows frequent discovery of better partitioning solutions by searching spaces overlooked by traditional SA cost functions. We present experimental results on a very large design space, where several thousand configurations are explored in minutes as compared to several hours or days using a traditional SA formulation. Furthermore, our approach is frequently able to locate better design points with over 10 % improvement in application execution time compared to the solutions generated by a Kernighan-Lin partitioning algorithm starting with an all-SW partitioning.

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Section: Resultsmentioning

confidence: 99%

Efficient search space exploration for HW-SW partitioning

Banerjee

Dutt

2004

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES+ISSS

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“…They proposed a partitioner driven by the closeness metrics, which provides the designer with a measure on how efficient a solution could be, one that implements two different components on the same side, HW or SW. This technique was further improved with a procedural partitioning [19,20]. Vahid and Gajski [19] proposed a set of closeness metrics for a functional partitioning at the system level.…”

Section: Reconfigurable Systems and Codesignmentioning

confidence: 99%

An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-dimensional Reconfigurable Architectures

Redaelli

Santambrogio

Memik

2008

2008 International Conference on Reconfigurable Computing and FPGAs

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This work proposes an exact ILP formulation for the task scheduling problem on a 2D dynamically and partially reconfigurable architecture. Our approach takes physical constraints of the target device that is relevant for reconfiguration into account. Specifically, we consider the limited number of reconfigurators, which are used to reconfigure the device. This work also proposes a reconfiguration-aware heuristic scheduler, which exploits configuration prefetching, module reuse, and antifragmentation techniques. We experimented with a system employing two reconfigurators. This work also extends the ILP formulation for a HW/SW Codesign scenario. A heuristic scheduler for this extension has been developed too. These systems can be easily implemented using standard FPGAs. Our approach is able to improve the schedule quality by 8.76% on average (22.22% in the best case). Furthermore, our heuristic scheduler obtains the optimal schedule length in 60% of the considered cases. Our extended analysis demonstrated that HW/SW codesign can indeed lead to significantly better results. Our experiments show that by using our proposed HW/SW codesign method, the schedule length of applications can be reduced by a factor of 2 in the best case.

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“…Different techniques exist to determine these values (e.g., [9] [20]). The method we adopted is based on a very fine characterization of elementary hardware building blocks (blocks that conduct very simple logical and arithmetic operations such as AND, OR, +, .…”

Section: Fitness Computationmentioning

confidence: 99%