Incremental techniques for the identification of statically sensitizable critical paths

Ju, Yun-Cheng; Saleh, R.

doi:10.1145/127601.127729

Cited by 62 publications

(25 citation statements)

References 14 publications

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“…Because the delay of P [s, v2, v3, v6] is greater than threshold T, the forward tracing will find the full path P [s, v2, v3, v6, t]. And this path is inserted into MKPATH [1]. The second iteration, backward tracing will trace back to v4.…”

Section: E Extracting the K-most Critical Paths At Multi-corner Multmentioning

confidence: 99%

“…Detecting and identifying a set of critical paths are crucial steps in timing analysis and optimization. There exist many techniques [1][2][3][4] of extracting critical paths followed by delay analysis of digital circuits. The depth-first search and breadth-first search [1] are two major critical path search algorithms.…”

Section: Introductionmentioning

confidence: 99%

“…There exist many techniques [1][2][3][4] of extracting critical paths followed by delay analysis of digital circuits. The depth-first search and breadth-first search [1] are two major critical path search algorithms. An efficient algorithm of detecting Kmost critical paths was proposed in [6] and the benefit comes from pruning unnecessary searches.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Extracting the K-most Critical Paths in Multi-corner Multi-mode for Fast Static Timing Analysis

Oh¹,

Jin²,

Kim³

2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Detecting a set of longest paths is one of the crucial steps in static timing analysis and optimization. Recently, the process variation during manufacturing affects performance of the circuit design due to nanometer feature size. Measuring the performance of a circuit prior to its fabrication requires a considerable amount of computation time because it requires multi-corner and multi-mode analysis with process variations. An efficient algorithm of detecting the K-most critical paths in multi-corner multi-mode static timing analysis (MCMM STA) is proposed in this paper. The ISCAS'85 benchmark suite using a 32 nm technology is applied to verify the proposed method. The proposed K-most critical paths detection method reduces about 25% of computation time on average.

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Section: E Extracting the K-most Critical Paths At Multi-corner Multmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Extracting the K-most Critical Paths in Multi-corner Multi-mode for Fast Static Timing Analysis

Oh¹,

Jin²,

Kim³

2016

JSTS:Journal of Semiconductor Technology and Science

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show abstract

“…Whether or not a path is long is determined by a designer-specified threshold. In our experiments, we used the efficient path extraction technique in [18], which allowed us to obtain sensitized paths in descending order of path length in a relatively short amount of time. In addition, we used 55% of the length of structurally longest path as the threshold.…”

Section: Sensitized Long Path Identificationmentioning

confidence: 99%

A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing

Miyase

Sakai

Wen

et al. 2013

IEICE Trans. Inf. & Syst.

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SUMMARYTest power has become a critical issue, especially for lowpower devices with deeply optimized functional power profiles. Particularly, excessive capture power in at-speed scan testing may cause timing failures that result in test-induced yield loss. This has made capturesafety checking mandatory for test vectors. However, previous capturesafety checking metrics suffer from inadequate accuracy since they ignore the time relations among different transitions caused by a test vector in a circuit. This paper presents a novel metric called the Transition-TimeRelation-based (TTR) metric which takes transition time relations into consideration in capture-safety checking. Detailed analysis done on an industrial circuit has demonstrated the advantages of the TTR metric. Capturesafety checking with the TTR metric greatly improves the accuracy of test vector sign-off and low-capture-power test generation.

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“…The set of critical nets contains edges on the current k-most critical paths. The placement algorithm has an integrated static timing analysis engine as well as a path enumeration algorithm [30]. The delay of the circuit (therefore slacks) and the set of the most critical paths are periodically updated based on the delay assigned to all current cut nets by the partitioning engine.…”

Section: Fig 4 Illustration Of Good and Bad Initial Linear Placementmentioning

confidence: 99%

Exploring Potential Benefits of 3D FPGA Integration

Ababei

Maidee

Bazargan

2004

Field Programmable Logic and Application

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A new timing-driven partitioning-based placement tool for 3D FPGA integration is presented. The circuit is first divided into layers with limited number of inter-layer vias, and then placement is performed on individual layers, while minimizing the delay of critical paths. We use our tool, which will be available on the web for the research community, as a platform for exploring potential benefits in terms of delay and wire-length that 3D technologies have to offer for FPGA fabrics. We show that 3D integration results in wire-length reduction for FPGA designs. However, unlike the ASIC case, wire-length reduction does not automatically translate to much smaller circuit delays, unless multi-segment lengths are employed between layers. Our empirical analysis shows that wire-length can be reduced by up to 50% (20% on average) using 5 layers. Delay reductions are estimated to be up to 30% (15% on average) using the same number of layers.

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Incremental techniques for the identification of statically sensitizable critical paths

Cited by 62 publications

References 14 publications

Extracting the K-most Critical Paths in Multi-corner Multi-mode for Fast Static Timing Analysis

Extracting the K-most Critical Paths in Multi-corner Multi-mode for Fast Static Timing Analysis

A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing

Exploring Potential Benefits of 3D FPGA Integration

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