Indirect testing of digital-correction circuits in analog-to-digital converters with redundancy

Lewis, S.H.; Ramachandran, R.; Snelgrove, W.M.

doi:10.1109/82.401166

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F the Digital Correction Circuit1

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Cited by 17 publications

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“…The correction process for the remaining 1.5-bit stages can be implemented by simple adder that is the same as the conventional digital correction circuit [6]. We can see that the digital correction logics have been simplified by the final 5-bit flash ADC.…”

Section: F the Digital Correction Circuitmentioning

confidence: 98%

A 140MS/s 10-bit pipelined ADC with a folded S/H stage

Lee

Liu

2009

2009 IEEE International Symposium on Circuits and Systems

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A 140MS/s 10-bit pipelined analog-to-digital converter (ADC) using a folded sample-and-hold (S/H) stage and a 5-bit flash ADC is presented. To conquer the limited linear swing range results from an operational amplifier (OP-AMP). The proposed folded S/H stage allows the ADC to operate in the linear swing range of an OP-AMP. Only 17 comparators are required for a 5-bit flash ADC. Corresponding digital correction codes are added. The single-phase triggering method is adopted and it saves half the number of shift/latch elements. This pipelined ADC has been fabricated in a 0.18um CMOS process. It dissipates 65mW for a supply voltage of 1.8V. The measured signal-to-noise-plus-distortion ratio (SNDR) is achieved 55.4 dB. The differential nonlinearity (DNL) and integral nonlinearity (INL) is 0.78-LSB and 0.98-LSB, respectively.

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Section: F the Digital Correction Circuitmentioning

confidence: 98%