Indium bump deposition for flip-chip micro-array image sensing and display applications

Manasson, A.; Bah, Mohamed; Desmarais, Brian; Douglass, D. H.; Outten, C.A.; Schumacher, Joshua; Robinson, Matthew; Zhang, Chen

doi:10.1117/12.2303735

Cited by 7 publications

(3 citation statements)

References 10 publications

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“…Observation under an optical microscope revealed a small graininess of evaporated indium columns. This corresponds to a high packing density of In atoms, which inhibits the oxidation of the material inside the column [ 10 ]. As a result, a high level of dimensional uniformity, as well as an easier reflow and bonding process, can be achieved.…”

Section: Resultsmentioning

confidence: 99%

“…Such short connections provide excellent electrical characteristics (e.g., smaller inductance), which is important for operation at very high frequencies [ 8 , 9 ]. The use of a dense packing of micrometer-sized indium bumps significantly increases the signal-to-noise ratio of the device, and can also decrease noise [ 10 , 11 ]. In addition, the low melting point of indium (156 °C) and high plasticity guarantees no structural damage to both the detector and mount/readout electronics [ 12 , 13 ].…”

Section: Introductionmentioning

confidence: 99%

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Indium-Based Micro-Bump Array Fabrication Technology with Added Pre-Reflow Wet Etching and Annealing

et al. 2021

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Indium-based micro-bump arrays, among other things, are used for the bonding of infrared photodetectors and focal plane arrays. In this paper, several aspects of the fabrication technology of micrometer-sized indium bumps with a smooth surface morphology were investigated. The thermal evaporation of indium has been optimized to achieve ~8 μm-thick layers with a small surface roughness of Ra = 11 nm, indicating a high packing density of atoms. This ensures bump uniformity across the sample, as well as prevents oxidation inside the In columns prior to the reflow. A series of experiments to optimize indium bump fabrication technology, including a shear test of single columns, is described. A reliable, repeatable, simple, and quick approach was developed with the pre-etching of indium columns in a 10% HCl solution preceded by annealing at 120 °C in N2.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Indium-Based Micro-Bump Array Fabrication Technology with Added Pre-Reflow Wet Etching and Annealing

et al. 2021

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“…The factor limiting the fine pitch of solders is solder extrusion [13], which is an uncontrolled reduction in the distance between bumps leading to electrical shorting, and therefore solders require a minimum stand-off distance. Although Manasson et al in [14] reveal the fabrication of very fine pitch of indium bumps through evaporation, it does not show the fine-pitch application of indium bumps through flip-chip bonding. Flip-chip bonding is the key process to determine whether fine-pitch joints can be attained without electrically shorting.…”

Section: Assembly Methodsmentioning

confidence: 96%

Nb-based superconducting silicon interconnect fabric for cryogenic electronics

Yang¹,

Hu²,

Zhang³

et al. 2021

Quantum Sci. Technol.

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Quantum computing for real world applications requires large arrays of qubits. This requires advanced integration technologies. In this work, we propose a simple integration method with fine interconnect pitch (10 μm) and close spacing that can overcome the large input and output (I/O) and high wiring level requirements of very large scale of quantum circuits. A system-on-wafer (SoW) packaging concept called superconducting silicon interconnect fabric (superconducting-IF), based on silicon interconnect fabric (Si-IF), is proposed, with the help of a Au interlayer technology onto the superconducting-IF. The fine-pitch and die-to-wafer-scale Au interlayer is the first demonstration of direct metal–metal thermocompression bonding (TCB) that is optimized for superconducting applications without the use of solders. The developed Au interlayer integration technology is demonstrated to be Josephson-junction-compatible (<150 °C), mechanically robust (>30 MPa), and electrically reliable down to 2 K. The mechanical strength of the Au interlayer integration method is optimized through shear tests with a shear force around 150 N on 2 × 2 mm2 dies. The transition temperature (Tc) of Nb, which is at 9 K, is experimentally verified to be unchanged after each fabrication process. Electrical and temperature cycling measurements on over 20 bonded dies of large-pitch Kelvin structures as well as fine-pitch daisy chain structures reveal reliable connections in the low-temperature regime. This work pushes quantum computing a step closer to realize its potential through 3D integration of a very large scale of quantum circuits with a high density of I/O (>10 000 per mm2) as well as high wiring capability and without introducing lossy amorphous dielectrics.

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Preparation and atmospheric wet-reflow of indium microbump for low-temperature flip-chip applications

et al. 2022

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Indium bump deposition for flip-chip micro-array image sensing and display applications

Cited by 7 publications

References 10 publications

Indium-Based Micro-Bump Array Fabrication Technology with Added Pre-Reflow Wet Etching and Annealing

Indium-Based Micro-Bump Array Fabrication Technology with Added Pre-Reflow Wet Etching and Annealing

Nb-based superconducting silicon interconnect fabric for cryogenic electronics

Preparation and atmospheric wet-reflow of indium microbump for low-temperature flip-chip applications

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