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This work aims to validate the feasibility of device-level analysis to reflect the effects of fabrication processes and operations, as contrasted with the conventional method of x-ray photoelectron spectroscopy (XPS), which is widely employed in amorphous oxide semiconductor thin-film transistors (TFTs) but analyzes film-level specimens. First, an analysis setup was introduced to determine the optimal x-ray target position for device-level XPS, where the intensity of channel components is maximized, through imaging XPS. Then, to demonstrate the effectiveness of this approach, the impact of channel composition and bias-stress was investigated through the implementation of device-level XPS on bottom-gate InGaZnO TFTs. The cationic composition ratios of the fabricated TFTs varied from 0.27:1:1.33 (In:Ga:Zn) and 0.28:1:2.21 when the subcycle of the Zn precursor increased by a factor of 1.5 in the atomic-layer deposition process. The device with a higher Zn ratio exhibited a more negative turn-on voltage and a twice larger subthreshold swing. These characteristics were validated from the comparisons in the relative amount of oxygen vacancies in O 1s of the channel and interface regions by 8.4%p and 5.6%p, respectively, between the devices. Furthermore, the electron trapping effect was verified for the devices subjected to a positive gate bias-stress of 3 MV/cm, as evidenced by the changes in the binding energy difference (0.35 eV) between the channel and gate insulator layers, in comparison to the non-stressed device. Consequently, this work demonstrates that device-level XPS can be an effective tool for understanding TFTs' characteristics in various ways beyond film-level analysis.
This work aims to validate the feasibility of device-level analysis to reflect the effects of fabrication processes and operations, as contrasted with the conventional method of x-ray photoelectron spectroscopy (XPS), which is widely employed in amorphous oxide semiconductor thin-film transistors (TFTs) but analyzes film-level specimens. First, an analysis setup was introduced to determine the optimal x-ray target position for device-level XPS, where the intensity of channel components is maximized, through imaging XPS. Then, to demonstrate the effectiveness of this approach, the impact of channel composition and bias-stress was investigated through the implementation of device-level XPS on bottom-gate InGaZnO TFTs. The cationic composition ratios of the fabricated TFTs varied from 0.27:1:1.33 (In:Ga:Zn) and 0.28:1:2.21 when the subcycle of the Zn precursor increased by a factor of 1.5 in the atomic-layer deposition process. The device with a higher Zn ratio exhibited a more negative turn-on voltage and a twice larger subthreshold swing. These characteristics were validated from the comparisons in the relative amount of oxygen vacancies in O 1s of the channel and interface regions by 8.4%p and 5.6%p, respectively, between the devices. Furthermore, the electron trapping effect was verified for the devices subjected to a positive gate bias-stress of 3 MV/cm, as evidenced by the changes in the binding energy difference (0.35 eV) between the channel and gate insulator layers, in comparison to the non-stressed device. Consequently, this work demonstrates that device-level XPS can be an effective tool for understanding TFTs' characteristics in various ways beyond film-level analysis.
Metal oxide thin film transistor has been widely used in flat panel display industry because of its low leakage current, high mobility and large area uniformity. Besides with the development of printed display technology, inkjet printing process can fabricate the customizable patterns on diverse substrates without the need for vacuum or lithography, can significantly reduce cost and has received more and more attention. In this paper, we fabricate a bottom gate bottom contact structure thin film transistor (TFT) with indium-zinc-tin-oxide (IZTO) semiconductor using inkjet printing process. The surface morphology of the printed IZTO film is modified by adjusting the solvent composition and solute concentration of the printing precursor ink. The experimental result show that the use of binary solvents can effectively overcome the coffee ring shape caused by the accumulation of solute edge during the volatilization process of a single solvent, and finally show a uniform and flat contour surface. Further increase in solute concentration is in favor of formation of convex surface topology. The reason for the formation of the flat surface of the oxide film is the balance between the inward Marangoni reflux of the solute and the outward capillary flow during volatilization. In addition, using binary solvents printed IZTO thin film transistor exhibit excellent electrical properties. The ratio of width/length=50/30 exhibit a high on-off ratio of 1.21×10<sup>9</sup>,a high saturation field-effect mobility of 16.6 cm<sup>2</sup>·V<sup>-1</sup>·s<sup>-1</sup>,a low threshold voltage of 0.84 V and subthreshold swing of 0.24 V/dec. The uniform and flat active layer thin film pattern can form good contact with the source leakage electrode, and the contact resistance of TFT devices with different width-to-length ratios is less than 1000 Ω, which can achieve the basic conditions of high mobility thin film transistors prepared by inkjet printing. Therefore, using mixture solvents provides a universal and facile way to print oxide films with desired surface topology and provide a visible path for inkjet printing of high-mobility thin film transistors.
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