Inexact Designs for Approximate Low Power Addition by Cell Replacement

Almurib, Haider A. F.; Kumar, T. Nandha; Lombardi, Fabrizio

doi:10.3850/9783981537079_0042

Cited by 62 publications

(57 citation statements)

References 8 publications

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“…Low power approximate binary adders are generally constructed by replacing the accurate FAs with approximate FAs. We consider five approximate mirror adders (AMA1, AMA2, AMA3, AMA4 and AMA5) [7], three approximate XOR/XNOR based full adders (AXA1, AXA2 and AXA3) [8] and three inexact adder cells (InXA1, InXA2 and InXA3) [9]. Table 1 shows the truth tables of the 11 considered approximate FAs, and their characteristics including Size (A), Power consumption (P), Delay (D), number of Erroneous outputs (E), which indicates the likelihood of at least one output (Cout or Sum) being wrong, and PDP.…”

Section: Approximate Fas and Compressorsmentioning

confidence: 99%

“…AMA5 and AXA1 exhibit the lowest and highest PDP, respectively. Figure 4 shows the number of transistors for each FA, as well the number of erronous [9].…”

Section: Approximate Fas and Compressorsmentioning

confidence: 99%

“…The transistor level approximation provides the highest flexibility due to the ability to tweak most of the design parameters at this level. Various approximate full adders (FA) at the transistor level have been proposed including the mirror adders [7], the XOR/XNOR based FA [8] and the inexact FA [9]. On the other hand, most of approximate multipliers have been designed at higher levels of abstraction, i.e., gate, RTL and application.…”

Section: Introductionmentioning

confidence: 99%

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Comparative Study of Approximate Multipliers

Masadeh

Hasan

Tahar

2018

Proceedings of the 2018 Great Lakes Symposium on VLSI

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Approximate multipliers are widely being advocated for energy-efficient computing in applications that exhibit an inherent tolerance to inaccuracy. However, the inclusion of accuracy as a key design parameter, besides the performance, area and power, makes the identification of the most suitable approximate multiplier quite challenging. In this paper, we identify three major decision making factors for the selection of an approximate multipliers circuit: (1) the type of approximate full adder (FA) used to construct the multiplier, (2) the architecture, i.e., array or tree, of the multiplier and (3) the placement of sub-modules of approximate and exact multipliers in the main multiplier module. Based on these factors, we explored the design space for circuit level implementations of approximate multipliers. We used circuit level implementations of some of the most widely used approximate full adders, i.e., approximate mirror adders, XOR/XNOR based approximate full adders and Inexact adder cell. These FA cells are then used to develop circuits for the approximate high order compressors as building blocks for 8x8 array and tree multipliers. We then develop various implementations of higher bit multipliers by using a combination of exact and inaccurate 8x8 multiplier cells. All these implementations have been done using the Cadence's Spectre tool with the TSMC65nm technology. The design space of these multipliers is explored based on their power, area, delay and error and the best approximate multiplier designs are identified. The report also presents the validation of our results using an image blending application. An open source library of implemented cells and multiplier circuits are available online.

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Section: Approximate Fas and Compressorsmentioning

confidence: 99%

“…AMA5 and AXA1 exhibit the lowest and highest PDP, respectively. Figure 4 shows the number of transistors for each FA, as well the number of erronous [9].…”

Section: Approximate Fas and Compressorsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Comparative Study of Approximate Multipliers

Masadeh

Hasan

Tahar

2018

Proceedings of the 2018 Great Lakes Symposium on VLSI

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“…In this letter, we propose a new approximate circuit design methodology in which we consider a set of different adder blocks to build a heterogeneous multiplier. We use the three approximate implementations of full adders proposed by [1] shown in Fig. 1 as possible adder implementations and explore the design space to converge to an optimal heterogeneous design.…”

Section: Related Workmentioning

confidence: 99%

A Novel Heterogeneous Approximate Multiplier for Low Power and High Performance

Alouani

Ahangari

Öztürk

et al. 2018

IEEE Embedded Syst. Lett.

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Approximate computing is a design paradigm considered for a range of applications that can tolerate some loss of accuracy. In fact, the bottleneck in conventional digital design techniques can be eliminated to achieve higher performance and energy efficiency by compromising accuracy. In this letter, a new architecture that engages accuracy as a design parameter is presented, where an approximate parallel multiplier using heterogeneous blocks is implemented. Based on design space exploration, we demonstrate that introducing diverse building blocks to implement the multiplier rather than cloning one building block achieves higher precision results. We show experimental results in terms of precision, delay, and power dissipation as metrics and compare with three previous approximate designs. Our results show that the proposed heterogeneous multiplier achieves more precise outputs than the tested circuits while improving performance and power tradeoffs.

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“…A variety of approximate adders have been proposed in the literature, with different levels of trade-offs between accuracy and performance. These adders can be classified as low-latency [1] (and references therein) and low-power approximate adders [2]- [7]. In this paper, our focus is power optimized implementations of signal processing algorithms using low power approximate adders (LPAA).…”

Section: Introductionmentioning

confidence: 99%

ErrorModelingLPAA.pdf

Dharmaraj¹,

Vasudevan²,

Chandrachoodan³

2019

Preprint

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Approximate circuit design has gained significance in recent years targeting error tolerant applications. In this paper, we consider the problem of minimizing the power for a given accuracy, in a signal processing application with accurate adders replaced by low-power approximate adders. We first demonstrate that the commonly used assumption that the inputs to the adder are uniformly distributed results in an inaccurate prediction of error statistics for multi-level circuits. To overcome this problem, we propose the use of parameterized error models for adders, with input static probabilities as parameters. The static probability computation in our work considers not just the functionality of the adder but also its position in the circuit, functionality of its parents and the number of approximate bits in the parent blocks. This parameterized error model can be incorporated in any optimization framework. We demonstrate up to 6.5 dB improvement in the accuracy of noise power prediction when the proposed model is used to optimize an 8 × 8 DCT.

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Inexact Designs for Approximate Low Power Addition by Cell Replacement

Cited by 62 publications

References 8 publications

Comparative Study of Approximate Multipliers

Comparative Study of Approximate Multipliers

A Novel Heterogeneous Approximate Multiplier for Low Power and High Performance

ErrorModelingLPAA.pdf

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