Influence of Accurate Electron Drift Velocity Modelling on the Electrical Characteristics in GaN-on-Si HEMTs

Reiser, Korbinian; Twynam, J.K.; Eckl, Christian; Weigel, Helmut BrechRobert

doi:10.1109/sispad.2019.8870417

Cited by 2 publications

(2 citation statements)

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“…To determine the dynamic delay density as well as all delay components, we perform a two-dimensional device simulation of an AlGaN/GaN HEMT with source-connected field plate for V D =20 V and I D =23 mA mm −1 . The simulated transconductance and output-conductance are g m =135 mS and g d =1.37 mS. More details on the models used and the simulation structure can be found in [16].…”

Section: Quasi-static Delay Simulationmentioning

confidence: 99%

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Delay analysis of high-electron mobility transistors under high drain bias

Reiser¹,

Twynam²,

Brech³

et al. 2020

Semicond. Sci. Technol.

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In this work, we present a new delay analysis of high-electron-mobility transistors (HEMTs), in which we show that the total intrinsic delay can be separated into six distinct contributions. We distinguish between delays caused by the capacitive coupling between electrodes, the quasi-static charge distribution within the device and a dynamic delay originating from on-state charge flow. An analytical expression for the dynamic delay is established in the form of a delay density using a position dependent image charge analysis. This delay density allows us to show graphically the position dependence of the delay contributions of mobile charge throughout the depletion region. Furthermore, the dynamic delay is separated into a component dependent on the length of the gate electrode and a drain delay component dependent on the drain voltage bias. The influence of high drain bias on the delay components is investigated with the aid of GaN HEMT device simulations and measurements, showing the relative importance of scaling the gate and the drain regions. The RF delay analysis reported here is based upon the definition of small-signal current gain and elucidates the effect of position dependent mobile charge within a HEMT, clarifying the requirements for device scaling.

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Section: Quasi-static Delay Simulationmentioning

confidence: 99%

“…For calibration off-chip SOLT as well as short and open on-wafer deembedding standards are used. More details on the structure and the fabrication can be found in [16]. For the measurements, the drain current is fixed at I D =23 mA mm −1 and the frequency is swept at various drain voltages V D .…”

Section: Delay Analysis Under High Drain Biasmentioning

confidence: 99%