Influence of Annealing Condition on TSV Pumping and Microstructure Evolution

Jing, Xiangmeng; Lee, Ui-hyoung; Chen, Xu; Niu, Zhongcai; Song, Changjian; Zhang, Wenqi; Bae, Jong-yong; Won, Jonghan

doi:10.1149/06604.0183ecst

Cited by 1 publication

(1 citation statement)

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“…These poly-Si metasurfaces were formed by conventional thermal annealing process at 950 °C for 5 h in order to reduce k by a factor of ten. However, high-temperature and long duration of thermal annealing may cause critical damages to underlying CMOS image sensor's circuits [10,11]. In this study, we focus on Si metasurfaces in the visible range (λ=450-650 nm) to make use of the highindex contrast and low light absorption on top of semiconductor circuits.…”

Section: Introductionmentioning

confidence: 99%

CMOS-compatible Si metasurface at visible wavelengths prepared by low-temperature green laser annealing

et al. 2018

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A low-temperature laser crystallization is newly devised for producing polycrystalline silicon (poly-Si) thin films of low-loss, low surface roughness enough for nanoscale patterning, applicable to practical Si metasurface elements on complementary metal-oxide semiconductor (CMOS) electronic architectures in visible lights. The method is based on dielectric encapsulation of an amorphous Si film and subsequent laser-induced local crystallization. Such poly-Si thin film yields order-of-magnitude smaller surface roughness and grain size than those obtained with the conventional laser annealing processes. The mechanism of the formation of small and uniform crystalline grains during solidification is studied to ensure the smooth surfaces enough for nanoscale patterning. By obtaining root mean square of surface roughness <2.49 nm and extinction coefficient <4.8×10 -2 at 550 nm, visible metasurface color-filter elements are experimentally demonstrated with the resonant transmission-peak efficiency approaching ∼85%. This low-loss poly-Si metasurface is favorably compatible with embedded CMOS electronic architectures in contrast to the conventional thermal annealing processes that often cause failure of electrical device functionalities due to delamination and material-property degradation problems. The proposed fabrication in this study provides a practical method for further development of various Si metasurfaces in the visible domain and their integration with CMOS electronic devices as well.

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Section: Introductionmentioning

confidence: 99%