Influence of die attachment on MOS transistor matching

Bastos, J.; Steyaert, Michiel; Pergoot, A.; Sansen, Willy

doi:10.1109/66.572070

Cited by 29 publications

(21 citation statements)

References 10 publications

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“…Large area devices have been designed to minimize device parameter variations. Critically matched transistors of the input differential stage are placed on the die's central axis where low stress gradients occur in order to minimize sensitivity to die stress [4].…”

Section: Proposed Amplifier Architecturementioning

confidence: 99%

Integrated Circuit Trimming Technique for Offset Reduction in a Precision CMOS Amplifier

Singh

Audet

Gagnon³

et al. 2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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This article presents an application of a recently reported IC trimming technique using laser diffused resistors to reduce the input referred offset voltage of a precision amplifier. A three stage precision CMOS operational amplifier topology is proposed utilizing laser-trimmable diffused resistors for postfabrication trimming. The amplifier is designed to operate over an industrial temperature range (-40 0 C to +85 0 C) including process corners and utilizes an on-chip CMOS bias generation circuit to maintain a robust performance. The results of post-layout simulation of the complete circuit are summarized. The effects of the trimming technique on the input offset voltage of the amplifier are described. The circuit is designed using the TSMC 0.18µm CMOS process and operates from a single supply of 3.3 V. P 709 1-4244-0921-7/07 $25.00 © 2007 IEEE.

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Section: Proposed Amplifier Architecturementioning

confidence: 99%

Integrated Circuit Trimming Technique for Offset Reduction in a Precision CMOS Amplifier

Singh

Audet

Gagnon³

et al. 2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…However, a large chip area can result in systematic errors. Examples of systematic errors are gradient errors [1], [2] and temperature gradients [3]. In [4], a switching sequence was proposed.…”

Section: Introductionmentioning

confidence: 99%

A Switching Sequence for Linear Gradient Error Compensation in the DAC Design

Kuo

2011

IEEE Trans. Circuits Syst. II

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A switching sequence is proposed to compensate for the linear gradient error in the current source array of currentsteering digital-to-analog converter (DAC). A systematic method is established to obtain a switching sequence for both 1-D and 2-D current source arrays. The proposed switching sequence is also validated by the mathematical induction and exhibits a minimum variance of error. The proposed switching sequence is implemented into a 10-bit DAC. Simulation results show that the proposed switching sequence performs with a better integral nonlinearity (INL) and differential nonlinearity (DNL) compared to those of other switching sequences. The DAC is fabricated in a 1P6M 0.18-μm 1.8-V CMOS process and consumes less than 25 mW of power. The measured INL and DNL of the fabricated 10-b DAC are less than 0.62 and 0.41 LSB, respectively.Index Terms-Digital-to-analog converter (DAC), segmentation architecture, switching sequence.

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“…The input-referred, OTA3 mismatch voltage given by (9) would increase to near the 1.1 mV measured value if this additional mismatch was included for each of the four device pairs. In [126,131,138,139,154], threshold voltage and transconductance factor distance mismatch is reported from experimental measurements. There is considerable variability in distance mismatch since it is a strong function of die attachment and stress [139,152].…”

mentioning

confidence: 94%

Optimizing Drain Current, Inversion Level, and Channel Length in Analog CMOS Design

Binkley

Blalock

Rochelle³

2006

Analog Integr Circ Sig Process

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This paper describes a methodology for selecting drain current, inversion level (represented by inversion coefficient), and channel length for optimum performance tradeoffs in analog CMOS design. Here, inversion coefficient replaces width as a design choice to permit a conscious optimization of inversion level while width is implicitly considered. Transconductance, gate-referred thermal-noise voltage, and drain-source saturation voltage are optimized towards weak inversion while transconductance linearity and drain-referred thermal-noise current are optimized in strong inversion. Voltage gain, flicker noise, and dc mismatch are optimized towards weak inversion at long channel length while bandwidth is optimized in strong inversion at short channel length. Optimization expressions are given along with measured transconductance efficiency and Early voltage from weak through strong inversion over a wide range of channel lengths. Transconductance efficiency and Early voltage are used as normalized measures of transconductance and drain-source resistance, independent of drain current. The methodology presented is used to design three 0.5-µm operational transconductance amplifiers having equal 50-µA bias currents, but different tradeoffs in gain, bandwidth, noise, and dc mismatch. The amplifiers have measured voltage gains of 16.8, 110, and 326 V/V, −3-dB bandwidths of 350, 51, and 5 MHz, input-referred flicker-noise voltage at 100 Hz of 2,000, 450, and 58 nV/Hz 1/2 , and input-referred dc mismatch voltages of 10.2, 2.2, and 1.1 mV respectively. The design methodology can be readily extended to deeper submicron CMOS processes.

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Influence of die attachment on MOS transistor matching

Cited by 29 publications

References 10 publications

Integrated Circuit Trimming Technique for Offset Reduction in a Precision CMOS Amplifier

Integrated Circuit Trimming Technique for Offset Reduction in a Precision CMOS Amplifier

A Switching Sequence for Linear Gradient Error Compensation in the DAC Design

Optimizing Drain Current, Inversion Level, and Channel Length in Analog CMOS Design

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