2013 14th International Conference on Electronic Packaging Technology 2013
DOI: 10.1109/icept.2013.6756632
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Influence of geometry of microbump interconnects on thermal stress and fatigue life of interconnects in copper filled through silicon via structure

Abstract: Through silicon via (TSV) is an emerging technology enabling three dimensional (3D) packaging through vertical interconnection between multiple chips, which can significantly increase I/O per unit area, reduce electrical resistance as well as RC delay, and miniaturize the solder interconnects. However, it can also dramatically increase the current density and thermal energy density in each interconnect meanwhile. Thus, the reliability of miniaturized interconnects should be paid more attention. In this study, … Show more

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Cited by 6 publications
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