Influence of Interface Traps and Surface Mobility Degradation on Scanning Capacitance Microscopy Measurement

Abstract

Abstract-Although scanning capacitance microscopy (SCM) is based on the MOS capacitance theory, the measurement frequency is 915-MHz instead of 100 kHz to 1 MHz in conventional MOS capacitance-voltage measurement. At this high frequency, the reactance of the probe tip-to-substrate capacitance can become smaller than the series resistance of the substrate inversion layer, particularly when the surface mobility is degraded. The response of the oxide-silicon interface traps to SCM measurement is also different due to the use of a 10-kHz signal to determine dC dV. In this paper, we compare experimental and simulation data to demonstrate the effects of interface traps and surface mobility degradation on SCM measurement. Implications on the treatment of SCM data for accurate dopant profile extraction are also presented.

Accurate modeling of the effects of fringing area interface traps on scanning capacitance microscopy measurement

“…In SCM dC/dV measurement when there are no interface traps, the change in capacitance, , in response to the change in voltage, , is simply the slope of the corresponding Curve 1 (with the assumption that the used to sense dC/dV is sufficiently small). When interface traps are present, because interface traps do not respond to the is the same as that of the sample if it is trap-free and held at the same surface potential [11] and not related to the slope of Curve 2. Theoretically the peak dC/dV, although occurring at different dc bias, would have the same magnitude regardless of the presence of interface traps.…”

“…In a previous publication, we have proposed the use of the measured accumulation-to-depletion peak dC/dV at every spatial point for dopant profile extraction [11]. This quantity is a direct function of the underlying semiconductor dopant concentration according to MOS physics.…”

Modeling the Effects of Interface Traps on Scanning Capacitance Microscopy dC/dV Measurement

“…From MOS capacitor theory, we expect to see identical peak dC/dV regardless of the presence of interface traps [11] if using the simulation technique described above. The fact that in Fig.…”

“…This causes the C-V characteristic of SCM to behave differently to a MOS capacitor. To avoid such discrepancy in the dopant profile extraction method using peak dC/dV as we proposed in [11], it is necessary to keep the interface trap densities minimum in the sample preparation processes. …”

“…However in the presence of interface traps which do not respond to the V ac signal [10,11], it is necessary to understand this effect on the SCM dC/dV signal. Also the effect of interface traps on the SCM measurement will not necessarily be the same as on a MOS capacitor, as the SCM probe has extremely small dimension and the charge from interface traps surrounding the probe is likely to have significant impact on SCM capacitance.…”