InGaAs channel MOSFET with self‐aligned source/drain MBE regrowth technology

Abstract

InGaAs is a promising alternative channel material to Si for sub‐22 nm node technology because of its low electron effective mass (m*) hence high electron velocities. We report a gate‐first MOSFET process with self‐aligned source/drain formation using non‐selective MBE re‐growth, suitable for realizing high performance scaled III‐V MOSFETs. A W/Cr/SiO2 gate stack was defined on thin (4 nm/2.5 nm) InGaAs/InP channel by an alternating selective dry etch technique. A 5 nm Al2O3 layer was used as gate dielectric. An InAlAs bottom barrier provided vertical confinement of the channel. An in‐situ H cleaning of the wafer leaves an epi‐ready surface suitable for MBE or MOCVD regrowth. Source/Drain region were defined by non‐selective MBE regrowth and in situ molybdenum contacts. First generation of devices fabricated using this process showed extremely low drive current of 2 μA/μm. The drive current was limited by an extremely high source resistance. A regrowth gap between source/drain and gate was the cause for high source resistance. The gap in the regrowth was because of low growth temperature (400 °C). A modified high temperature growth technique resolved the problem. (© 2009 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

InGaAs MOSFET source structures toward high speed/low power applications

“…Thus, InGaAs regrown sources were reported [8][9][10][11] and selective regrowth was required. On the other hand, when we used an n-InP source, a structure similar to the InGaAs-raised structure was fabricated by using single epitaxial growth and InP selective etching.…”

$\hbox{In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}$ Channel MOSFETs With Self-Aligned InAs Source/Drain Formed by MEE Regrowth

“…As deposited, the Mo film covered the entire wafer surface, bridging over the dielectric-encapsulated gate, and therefore short circuited the source and drain electrodes. This source/drain contact metal covering the gate electrode was therefore removed with heightselective etch [9]. Source/drain pads were then deposited, and devices are mesa isolated.…”

“…W (50 nm)/Cr (50 nm)/SiO 2 (350 nm) gates were then defined by optical lithography at gate lengths varying from 200 nm to 10 μm and were patterned using a selective dry etch process [9]. The 20-25-nm-thick SiN x sidewalls were then defined by blanket PECVD deposition and low-power anisotropic RIE etch.…”

“…The devices were fabricated following the process flow in [9]. A 1 × 10 17 cm −3 Be-doped (P-type) In 0.48 Al 0.52 As buffer layer, an In 0.48 Al 0.52 As bottom confinement layer and a 5-nmthick In 0.53 Ga 0.47 As channel were grown by MBE upon a p + InP substrate.…”

“…In these devices, metal contacts to the source and drain n + regions are also self-aligned to the gate. These are formed by depositing Mo contact metal in situ immediately after regrowth, followed by patterning by height-selective etching [9]. In contrast to earlier results [10] reported using In 0.53 Ga 0.47 As regrown source/drain regions, the InAs n + regions employed here are less prone to electron depletion from defects or surface states in comparison to In 0.53 Ga 0.47 As because the intrinsic Fermi level pinning is above the conduction band edge [11].…”