2004
DOI: 10.1109/led.2004.835160
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InGaAs–InP Metamorphic DHBTs Grown on GaAs With Lattice-Matched Device Performance and<tex>$f_tau$</tex>,<tex>$f_max≫268$</tex>GHz

Abstract: InP-In 0 53 Ga 0 47 As-InP double heterojunction bipolar transistors (DHBTs) were grown on a GaAs substrate using a metamorphic buffer layer and then fabricated. The metamorphic buffer layer is InP-employed because of its high thermal conductivity to minimize device heating. An and max of 268 and 339 GHz were measured, respectively-both records for metamorphic DHBTs. A 70-nm SiO 2 dielectric sidewall was deposited on the emitter contact to permit a longer InP emitter wet etch for increased device yield and red… Show more

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Cited by 13 publications
(9 citation statements)
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“…The structure of InGaAs MM-PINPD is similar as previous reports except the whole structure were grown on semiinsulating substrate [11]. The metamorphic buffer absorbs the strain of lattice mismatch and prevents the vertical propagation of dislocations, thereby maintaining the quality of the device active layers.…”
Section: Resultsmentioning
confidence: 96%
“…The structure of InGaAs MM-PINPD is similar as previous reports except the whole structure were grown on semiinsulating substrate [11]. The metamorphic buffer absorbs the strain of lattice mismatch and prevents the vertical propagation of dislocations, thereby maintaining the quality of the device active layers.…”
Section: Resultsmentioning
confidence: 96%
“…The structure of InGaAs MM-PINPD is similar as previous reports except the whole structure was grown on semi-insulating substrate [15]. The metamorphic buffer absorbs the strain of lattice mismatch and prevents the vertical propagation of dislocations, thereby maintaining the quality of the device active layers.…”
Section: Resultsmentioning
confidence: 98%
“…The heteroepitaxy of III-V alloys, lattice-matched to InP, onto mismatched substrates, such as GaAs and Si substrates, have drawn much attention for both electronic and optoelectronic applications. These material combinations take advantage of a lower substrate cost and epitaxial growth on larger available wafer, as well as for the compatibility with the existing high volume Si-based CMOS technology and monolithic integration onto the Si-based optoelectronic platform [1][2][3][4][5][6][7][8][9]. However, the high defect density, originating from the large mismatch in either lattice constant and/or thermal expansion coefficient [10] between GaAs/InP or Si/InP, has remained as a challenging factor limiting the device performance and reliability [11].…”
Section: Introductionmentioning
confidence: 99%