InP-based logic gates for low power monolithic optoelectronic circuits [InGaAs/InAlAs/InP]

Brennemann, A.; Bushehri, E.; Daumann, W.; Agethen, M.; Bertenburg, R.M.; Brockerhoff, W.; Staroselsky, V.; Bratov, V.; Schlichter, T.; Tegude, F.-J.

doi:10.1109/icecs.1998.814016

Cited by 2 publications

(2 citation statements)

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Section: Introductionmentioning

confidence: 99%

“…Monolithic receivers with data rates above 20 Gb/s have already been realized in InP [l]. The next step is the implementation of digital circuits for further data processing, monolithically integrated with the front-end receiver itself [2].Due to the low Schottky-barrier of InAlAs lattice-matched to InP, the simultaneous fabrication of enhancement-and depletion-type HFETs requires highly sophisticated process technology. Therefore, Source Coupled FET Logic (SCFL) based on depletion-type HFETs is commonly applied.…”

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An 11-stage ring oscillator with nonlinear negative feedback for high speed digital applications

Brennemann

Bushehri

Agethen³

et al.

Conference Proceedings. 2000 International Conference on Indium Phosphide and Related Materials (Cat. No.00CH37107)

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This paper presents the performance of an 1 l-stage ring oscillator for high speed digital circuits using a gate configuration with nonlinear negative feedback (NNFB). An additional transistor is introduced into the switching path of buffered FET logic (BFL) gate to reduce the logic HIGH level, thus limiting the logic swing.As the result, switching speed of the circuits is improved by about 50 % compared to conventional BFL gates, while maintaining almost the same power consumption. The performance of this logic design approach is demonstrated by an e-beam written 1 1 -stage ring-oscillator using InP-based depletion-type heterostructure field effect transistors (DHFET). The oscillation frequency is 3.36 GHz corresponding to a delay time of 13.5 ps per gate. I IntroductionIn high data rate communication, specifically in the field of fibre optic transmission, the InP based material system is of particular interest due to its unique ability to provide devices for transmitting and receiving optical signals in the 1.55 ym range as well as high speed electronic devices. Monolithic receivers with data rates above 20 Gb/s have already been realized in InP [l]. The next step is the implementation of digital circuits for further data processing, monolithically integrated with the front-end receiver itself [2].Due to the low Schottky-barrier of InAlAs lattice-matched to InP, the simultaneous fabrication of enhancement-and depletion-type HFETs requires highly sophisticated process technology. Therefore, Source Coupled FET Logic (SCFL) based on depletion-type HFETs is commonly applied. The gates are used for the implementation of multiplexer ICs operating up to 80 Gb/s [3]. Several other components such as demultiplexers, decision circuits and frequency dividers for 40 Gb/s data transmission systems have already been realized [4].Despite the technological difficulties, the integration of enhancement and depletion type HFETs for Direct Coupled FET Logic (DCFL) gates has been demonstrated [5]. Based on 0.5 pm gate-length transistors, an 1 l-stage ring oscillator with an oscillation frequency of about 2 GHz was produced [6].In this paper a logic gate configuration is presented using depletion mode InGaAs/InAlAs/InP HFETs (DHFET). A Nonlinear Negative Feedback (NNFB) has been implemented into the design of Buffered FET Logic (BFL) gates in order to achieve increased operating speed. This gate was simulated and optimized with respect to speed, then an Il-stage ringoscillator was fabricated in InP using the same layer stack as for the traveling wave amplifier of the optoelectronic receiver, provided in [ 11. The following sections of this paper describe the circuit design and performance evaluation of the NNFB gates and the technological realization of the ring oscillator. Finally, measurement results of the ring oscillator are shown demonstrating the feasibility of the gate for high speed data transmission applications. I1 Circuit Design Fig. 1.a shows the standard Buffered FET inverter using two supply voltages of VDD = 1.8 V and...

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Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%