Input-Aware Implication Selection Scheme Utilizing ATPG for Efficient Concurrent Error Detection

Abstract

Recently, concurrent error detection enabled through invariant relationships between different wires in a circuit has been proposed. Because there are many such implications in a circuit, selection strategies have been developed to select the most valuable implications for inclusion in the checker hardware such that a sufficiently high probability of error detection ( P d e t e c t i o n ) is achieved. These algorithms, however, due to their heuristic nature cannot guarantee a lossless P d e t e c t i o n . In this paper, we develop a new input-aware implication selection algorithm with the help of ATPG which minimizes loss on P d e t e c t i o n . In our algorithm, the detectability of errors for each candidate implication is carefully evaluated using error prone vectors. The evaluation results are then utilized to select the most efficient candidates for achieving optimal P d e t e c t i o n . The experimental results on 15 representative combinatorial benchmark circuits from the MCNC benchmarks suite show that the implications selected from our algorithm achieve better P d e t e c t i o n in comparison to the state of the art. The proposed method also offers better performance, up to 41.10%, in terms of the proposed impact-level metric, which is the ratio of achieved P d e t e c t i o n to the implication count.

A Fault Tolerant Voter for Approximate Triple Modular Redundancy

“…If a fault is not masked, it will lead to an erroneous output of the function module. In brief, the manifestation of a fault is construed to be an error [7,8]. Fault tolerance is augmented into the system for the purpose of fault masking through the inclusion of redundancy techniques such as Triple Modular Redundancy (TMR) [9].…”