Input current ripple reduction through interleaving in single-supply multiple-output dc-dc converters

Schuck, Marcel; Pilawa-Podgurski, Robert C. N.

doi:10.1109/compel.2013.6626436

Cited by 14 publications

(10 citation statements)

References 13 publications

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“…Consequently, suitable angles cannot be found and the non-zero minimum of the cost function (Eq. (11)) is obtained at phase-shift angles of either 0 • or 180 • , as has been shown in [32]. This ensures that the expression in the cost function that corresponds to the imaginary part of the phasors is kept at zero.…”

Section: Visualization For N =mentioning

confidence: 98%

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Ripple Minimization Through Harmonic Elimination in Asymmetric Interleaved Multiphase DC–DC Converters

Schuck

Pilawa-Podgurski

2015

IEEE Trans. Power Electron.

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Symmetric multiphase dc-dc converters are widely used in power electronics, as they enable the processing of high power through splitting the overall load-current into multiple phases. Distributing the processed power symmetrically between the phases and performing ripple minimization through interleaving is well understood. However, in recent applications such as maximum power point (MPP) tracking for solar photovoltaic (PV), converters are forced to operate under asymmetric conditions, due to differences in the sources or loads of each converter. This work presents a control technique, based on harmonic elimination, that allows for ripple minimization under asymmetric conditions. The mathematical derivations are outlined and simulations are used to evaluate the performance of the proposed technique. Measurements taken from an experimental prototype, consisting of three dc-dc buck converters, demonstrate significant improvements in ripple reduction over conventional interleaving techniques. When the multi-phase converter is operated at the optimum asymmetric phase-shift found through the techniques presented here, a more than 3x reduction in net current ripple is observed under realistic operating conditions. Additionally, the undesirable first harmonic ripple component is reduced by 14.8 dB with the proposed technique.

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Section: Visualization For N =mentioning

confidence: 98%

“…Additional simulation results using the circuit simulator LTspice have been presented in [30] and [32]. The three-phase buck converter topology shown in Fig.…”

Section: Performance Evaluation By Simulationmentioning

confidence: 99%

Ripple Minimization Through Harmonic Elimination in Asymmetric Interleaved Multiphase DC–DC Converters

Schuck

Pilawa-Podgurski

2015

IEEE Trans. Power Electron.

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“…The power can be stored in the form of DC in a battery and converted to AC as needed to power the critical backup loads. When the flat DC battery power is sliced and boosted to higher DC link voltage by DC-DC converter and then it is again converted similar to an alternator output sine signature waveform [18]- [20]. The source of the ripple waveform characteristics is theoretically analyzed and depicted in Figure 2.…”

Section: Root Cause Analysis Of the Ripple Generation And Ripple Redu...mentioning

confidence: 99%

Optimization of passive filter components through active filtering of current ripple reduction in an inverter

Ramakrishnan

Ravi²

2022

IJPEDS

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This paper employs the active input current filtering concept developed and explained to optimize the conventional passive filter components in a two-stage telecommunication inverter. A prototype inverter has been designed for a rated power of 800 W. Optimization of the passive filter components consisting of inductance inductors tank (LTank) and capacitance capacitors tank (CTank) was performed through simulations. The simulation model used for this optimization was validated using the developed prototype. The focus of this work is to limit the input direct current (DC) current ripple within the limits specified in European Telecommunications Standards Institute (ETSI) 300132-2 for a battery supplied telecommunication inverter and optimize the passive filter components. Using the active filtering technique, limit the input current ripple and simultaneously reducing the filter capacity in DC-link. This advantage of active filtering technology over the conventional passive inductors and capacitors (LC) filter concept is explored and demonstrated in this paper.

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“…Another situation involves digital systems requiring separate supply rails for different circuit blocks, such as distributed power architectures (DPA) and low voltage CMOS power management systems [31,37]. Portable applications in particular have driven the development of systems requiring different voltage domains for various sub-systems to finely tune the operating voltage to minimize power consumption of each individual circuit block [38].…”

Section: Shortcomings Of Symmetric Interleavingmentioning

confidence: 99%

“…To verify the efficacy of the proposed ripple reduction method of [37] and to validate the proposed control method, simulations in MATLAB and LTSpice were carried out to closely emulate the hardware resolution limitations of the prototype converter. The buck topology of Fig.…”

Section: Chapter 4 Verification Of Implementation Technique 41 Simulmentioning

confidence: 99%

Asymmetric interleaving in low-voltage CMOS power management with multiple supply rails

Schuck

Pilawa-Podgurski

2014

2014 IEEE Energy Conversion Congress and Exposition (ECCE)

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Recent years have seen the proliferation of electronic devices that require multi-phase power converters to provide heterogeneous power rails to different systems. Typical systems will utilize symmetric interleaving as a method of reducing the input current ripple for the power converter. Asymmetric interleaving is a method of control that allows for a further reduction, and in some cases complete cancellation, of this input current ripple. This work looks at some of the challenges for a practical implementation using digital control, and provides results to quantify this improvement. This work demonstrates a control algorithm implementation capable of achieving nearly 3x reduction in the input current ripple via the asymmetric interleaving method.

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Input current ripple reduction through interleaving in single-supply multiple-output dc-dc converters

Cited by 14 publications

References 13 publications

Ripple Minimization Through Harmonic Elimination in Asymmetric Interleaved Multiphase DC–DC Converters

Ripple Minimization Through Harmonic Elimination in Asymmetric Interleaved Multiphase DC–DC Converters

Optimization of passive filter components through active filtering of current ripple reduction in an inverter

Asymmetric interleaving in low-voltage CMOS power management with multiple supply rails

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