Input-Splitting of Large Neural Networks for Power-Efficient Accelerator with Resistive Crossbar Memory Array

Kim, Yulhwa; Ahn, Daehyun; Kim, Jae‐Joon

doi:10.1145/3218603.3218605

Cited by 24 publications

(8 citation statements)

References 10 publications

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“…To perform an OPA operation with 16-bit inputs, naively increasing the DAC resolution is infeasible because DAC power consumption grows rapidly with resolution (N ) as: [17] (…”

Section: Bit Slicing the Opa Operationmentioning

confidence: 99%

PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-efficient ReRAM

Ankit¹,

Hajj²,

Chalamalasetti³

et al. 2019

Preprint

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The wide adoption of deep neural networks has been accompanied by ever-increasing energy and performance demands due to the expensive nature of training them. Numerous special-purpose architectures have been proposed to accelerate training: both digital and hybrid digital-analog using resistive RAM (ReRAM) crossbars. ReRAM-based accelerators have demonstrated the effectiveness of ReRAM crossbars at performing matrix-vector multiplication operations that are prevalent in training. However, they still suffer from inefficiency due to the use of serial reads and writes for performing the weight gradient and update step. A few works have demonstrated the possibility of performing outer products in crossbars, which can be used to realize the weight gradient and update step without the use of serial reads and writes. However, these works have been limited to low precision operations which are not sufficient for typical training workloads. Moreover, they have been confined to a limited set of training algorithms for fully-connected layers only.To address these limitations, we propose a bit-slicing technique for enhancing the precision of ReRAM-based outer products, which is substantially different from bit-slicing for matrix-vector multiplication only. We incorporate this technique into a crossbar architecture with three variants catered to different training algorithms. To evaluate our design on different types of layers in neural networks (fully-connected, convolutional, etc.) and training algorithms, we develop PANTHER, an ISA-programmable training accelerator with compiler support. Our design can also be integrated into other accelerators in the literature to enhance their efficiency. Our evaluation shows that PANTHER achieves up to 8.02×, 54.21×, and 103× energy reductions as well as 7.16×, 4.02×, and 16× execution time reductions compared to digital accelerators, ReRAM-based accelerators, and GPUs, respectively.

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“…To perform an OPA operation with 16-bit inputs, naively increasing the DAC resolution is infeasible because DAC power consumption grows rapidly with resolution (N ) as: [17] (…”

Section: Bit Slicing the Opa Operationmentioning

confidence: 99%

PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-efficient ReRAM

Ankit¹,

Hajj²,

Chalamalasetti³

et al. 2019

Preprint

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show abstract

“…For the neural network-hardware co-design, we adopt the input splitting methodology proposed in [9]. Overall architecture of the proposed design is shown in Fig.…”

Section: A Network Reconstructionmentioning

confidence: 99%

Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators

Kim,

Kim

2018

Preprint

Self Cite

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Recently, RRAM-based Binary Neural Network (BNN) hardware has been gaining interests as it requires 1-bit sense-amp only and eliminates the need for high-resolution ADC and DAC. However, RRAM-based BNN hardware still requires high-resolution ADC for partial sum calculation to implement large-scale neural network using multiple memory arrays. We propose a neural network-hardware co-design approach to split input to fit each split network on a RRAM array so that the reconstructed BNNs calculate 1-bit output neuron in each array. As a result, ADC can be completely eliminated from the design even for large-scale neural network. Simulation results show that the proposed network reconstruction and retraining recovers the inference accuracy of the original BNN. The accuracy loss of the proposed scheme in the CIFAR-10 testcase was less than 1.1% compared to the original network. The code for training and running proposed BNN models is available at: https://github.com/YulhwaKim/RRAMScalable BNN.

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“…Some works focus on how to split the weight matrix to reduce the ADC resolution requirement. Kim et al [7] improved the ReLU function to reduce the ADC resolution requirement from 8 to 4 bit [7]; however, this article did not consider ADC variation [8] and used a very large crossbar (512 × 512), which may cause considerable accuracy degradation. Tang et al [9] proposed to deploy a trained BNN network by splitting weights and mapping to multiple crossbar array with a 4-bit ADC [9].…”

Section: Introductionmentioning

confidence: 99%

A Relaxed Quantization Training Method for Hardware Limitations of Resistive Random Access Memory (ReRAM)-Based Computing-in-Memory

Wei

Jhang

Chen

et al. 2020

IEEE J. Explor. Solid-State Comput. Devices Circuits

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Nonvolatile computing-in-memory (nvCIM) exhibits high potential for neuromorphic computing involving massive parallel computations and for achieving high energy efficiency. nvCIM is especially suitable for deep neural networks, which are required to perform large amounts of matrix-vector multiplications. However, a comprehensive quantization algorithm has yet to be developed, which overcomes the hardware limitations of resistive random access memory (ReRAM)-based nvCIM, such as the number of I/O, word lines (WLs), and ADC outputs. In this article, we propose a quantization training method for compressing deep models. The method comprises three steps: input and weight quantization, ReRAM convolution (ReConv), and ADC quantization. ADC quantization optimizes the error sampling problem by using the Gumbel-softmax trick. Under a 4-bit ADC of nvCIM, the accuracy only decreases by 0.05% and 1.31% for the MNIST and CIFAR-10, respectively, compared with the corresponding accuracies obtained under an ideal ADC. The experimental results indicate that the proposed method is effective for compensating the hardware limitations of nvCIM macros. INDEX TERMS Compression, computing-in-memory (CIM), deep learning, quantization, resistive random access memory (ReRAM).

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Input-Splitting of Large Neural Networks for Power-Efficient Accelerator with Resistive Crossbar Memory Array

Cited by 24 publications

References 10 publications

PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-efficient ReRAM

PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-efficient ReRAM

Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators

A Relaxed Quantization Training Method for Hardware Limitations of Resistive Random Access Memory (ReRAM)-Based Computing-in-Memory

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