Inserting DVFS Code in Hard Real-Time System Tasks

Pinheiro, Diego; Gonçalves, Rawlinson S.; Valentin, Eduardo; Oliveira, Horacio de; Barreto, Raimundo

doi:10.1109/sbesc.2017.10

Cited by 4 publications

(4 citation statements)

References 5 publications

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“…They proposed that the most energy-efficient processor clock frequency is below the designed maximum frequency, and the relationship between the energy consumption and frequency presents a U-shaped curve. In addition, because the voltage transitions can require time on the order of tens of microseconds [32], Jiangwei et al [33], Pinheiro et al [34], and Kuehn et al [35] pointed out that the operation of processor frequency scaling can also introduce additional energy consumption because of the transition time overhead.…”

Section: Related Workmentioning

confidence: 99%

“…Our first assumption was that a higher processor frequency leads to more power consumption but a shorter execution time, so in the case of computationally intensive tasks, a higher processor clock frequency may not necessarily mean more energy consumption. In [32][33][34][35], it was pointed out that some widely used low-power technologies such as DVFS and power modes may have heavy overheads of transitions. We want to figure out a way to determine the application scenarios of different low-power technologies, so that microcontrollers can always run in the most energy-efficient way.…”

Section: Our Assumptionsmentioning

confidence: 99%

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An Energy-Efficient Strategy for Microcontrollers

Chen

Weng

2021

Applied Sciences

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Power saving has always been an important research direction in the field of microcontrollers. Dozens of low power technologies have been proposed to achieve the goal of reducing their power consumption. However, most of them focus mostly on lowering the consumption rate. It is well known that energy is the integral of power over time. Thus, our view is that both power and time should be carefully considered to achieve better energy efficiency. We reviewed some commonly used low power technologies and proposed our assumptions and strategy for improving energy efficiency. A series of test sets are designed to validate our hypotheses for improving energy efficiency. The experimental results suggest that time has no less impact on energy consumption than power. To support the operation of the processor, some peripheral components consume a constant amount of power regardless of the clock frequency, but the power consumption will be reduced when the processor enters low-power modes. This results in some interesting phenomena that are different from the usual thinking that energy can be saved by increasing processor clock frequency. For STM32F407 and Xtensa LX6 processors, this article also analyzes and calculates the minimum sleep time required for achieving energy saving based on our analytical models. Our energy efficiency strategy has been verified, and in some cases, it can indeed improve energy efficiency. We also proposed some suggestions on hardware design and software development for better energy efficiency.

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Section: Related Workmentioning

confidence: 99%

Section: Our Assumptionsmentioning

confidence: 99%

An Energy-Efficient Strategy for Microcontrollers

Chen

Weng

2021

Applied Sciences

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“…But the slack time exploited in work [13] was provided by intertask interferences of load operations but not execution paths, which makes a difference to our research. Recently, Pinheiro et al in [14] proposed a new combination of inter and intra-task approaches for energy saving with DVFS technique, but the idea of intratask DVFS was from RWEP in [5]. In contrast to the above, this work exploits the optimal DVFS scheduling in terms of a single task.…”

Section: Related Workmentioning

confidence: 99%

“…The static power is dissipated due to the leakage current, while the dynamic component occurs when the circuit is switching. Since latter term is usually the dominant term in most very large scale integrations (VLSIs), we consider applying DVFS technique to reduce the dynamic dissipation in this work, as in [5]- [7] and [14]. However, it is noteworthy that the static power also has a linear relationship with the supply voltage, thus scaling voltage/frequency to reduce the dynamic dissipation also has a positive impact on decreasing the static dissipation.…”

Section: Intra-task Dvfs Scheduling a Energy Modelmentioning

confidence: 99%

Energy-Efficient Intra-task DVFS Scheduling Using Linear Programming Formulation

et al. 2019

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In real-time embedded systems, minimizing energy consumption is one of the most important tasks. Intra-task dynamic voltage and frequency scaling (DVFS) has been the subject of much research in the task boundary of time-constrained applications for energy reduction. The problem of optimizing energy consumption with respect to intra-task DVFS scheduling can be addressed by assigning proper operational frequencies to individual basic blocks in a program while guaranteeing the deadline. Based on the profile information of a task, we first formulate the problem in terms of integer linear programming (ILP) regarding different assumptions of transition overhead. To verify the effectiveness of ILP formulations, the most representative intra-task DVFS techniques are taken for comparisons. The results of the experiments demonstrate that the proposed ILP method achieves greater energy savings than the existing approaches. Moreover, it determines the optimal scheduling strategy in reasonable execution time for applications with a limited number of blocks. INDEX TERMS Intra-task DVFS technique, time constrained applications, minimize energy consumption, ILP formulations.

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