Insights on memory controller scaling in multi-core embedded systems

Abstract

Abstract:In recent years, the growth on the number of cores as well as the frequency of cores along different processor generations has proportionally increased bandwidth needs simultaneously in both CPU and GPU systems. In order to address the communication latency between CPU and GPU memories in recent implementation of heterogeneous mobile embedded systems with hard or firm real-time requirements, sharing the same address space adds significant levels of contention. In addition, when heterogeneous cores are simultaneously present in a single system, memory parallelism is significantly restricted by a small amount of memory controllers (MCs). As a strategy to approach these significant levels of memory pressure, it is proposed in this paper evaluations of the impact of scaling MCs up to 4-8 units -limited by motherboard size for embedded purposes. Our findings show that performance is enhanced by a factor of 4x when employing only CPU cores, 4.6x when only GPU cores and finally, 2x when both CPU and GPU cores are simultaneously considered.

RAMON: Region-Aware Memory Controller

“…• Revisiting the operating system (OS) concept of address space used by Marino and Li's report [15], in RAM ON the novel concept of region is defined as an address space range dedicated to different sets of cores (CPU, GPU, or both), caches and respective interconnection. The inclusion of the two latter elements differentiate RAM ON from Non Uniform Memory Access (NUMAnode) mechanism in Linux OS.…”

“…• An evaluation on system implications for larger numbers of MCs in heterogeneous regions via using opticaland RF-based interfaces (signal modulation) rather than traditional digital transmission (where, to transmit a "0" or a "1", the whole line should be entirely set to the respective level) developed in [15].…”

“…• The methodology utilized to determine the performance when CPUs and GPUs are combined is an improved version over the proposed in [15]. The methodology consists of running each simulator (CPU and GPU) independently in regions that contain the maximum number of MCs allocated to each one.…”

Implications of shallower memory controller transaction queues in scalable memory systems

“…In addition, methods that combine DVFS [22] to shallower transaction queues under different memory traffic intensities and applications are likely to be considered. Furthermore, heterogeneous systems [30] offer interesting opportunities to evaluate transaction queue size reduction.…”

Hardware acceleration of de novo genome assembly

“…For example, assembly of human genome using PASHA software took around 21 hours on a 8-core workstation with 72 GB memory (Liu et al, 2011). Hardware accelerators like GPU and FPGAs are used along with processors to reduce this execution time by running the program on multiple computation units in parallel (Lin and Lin, 2014;Okuyama et al, 2012;Halstead et al, 2014;Marino and Li, 2014). Some bioinformatics applications along with assembly programs have been accelerated by FPGA-based accelerators.…”