Instability mechanisms for the hydrogenated amorphous silicon thin-film transistors with negative and positive bias stresses on the gate electrodes

Abstract

The hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs) with silicon nitride as a gate insulator have been stressed with negative and positive bias to realize the instability mechanisms. It is found that the threshold voltages of the a-Si:H TFTs are positively shifted under low negative bias stress and then negatively shifted for large negative gate bias. The positive threshold voltage shift is ascribed to the increased states in the band gap near the conduction band by the negative gate bias. As the negative bias continuously increases, the hole trapping in the silicon nitride or at the a-Si:H/silicon nitride interface will become dominant, resulting in the negative threshold voltage shift. A similar turnaround phenomenon is also observed with respect to the stress time. On the other hand, for the TFTs stressed with positive gate bias, the monotonic increase of the threshold voltage shift with stress time is attributed to the state creation. Nevertheless, the distributions of the created states in the energy band gap for the a-SiH TFTs after the stress will be affected by the bias polarity based on the defect pool model, reflecting the asymmetrical subthreshold swing change against the positive and negative stress bias.

The Instability Mechanisms of Hydrogenated Amorphous Silicon Thin Film Transistors under AC Bias Stress

“…The instability causes of the distortions of the transfer curves can be identified as the combination of charge trapping in the SiN x gate insulator and states created in the band gap of the a-Si:H layer. These phenomena have also been reported under DC bias stress by Tai et al 11) The dominant mechanism at the bias stress can be determined by the electrical characteristics of devices after applying a gate bias stress. In order to clarify the instability caused by the AC bias stress, the time dependence of the threshold voltage shift and the subthreshold swing change, compared with DC bias stress, are shown in Figs.…”

“…Thus, the compensation effect becomes more apparent. The mechanism of compensation between state creation and charge trapping was reported by Tai et al 11) It is worth noting that the same effective stress as of the DC bias stress. Moreover, the subthreshold swing change for the negative AC bias stress is larger than that for the positive AC bias stress.…”

“…In addition to practical applications, the fundamental physics of a-Si:H and SiN x in a-Si:H TFTs, e.g., the instabilities of a-Si:H TFTs under DC bias stresses, are of great interest and have been extensively researched to realize the instability mechanisms of a-Si:H TFTs. [3][4][5][6][7][8][9][10][11][12] The instabilities of devices can limit their functions in some demanding applications and have been studied extensively to identify the physical mechanisms. In a-Si:H TFTs, the two important instability characteristics are the threshold voltage (V th ) shift and subthreshold swing (S) behavior observed after a prolonged performance of the gate bias stress.…”

Low-Power a-Si:H Gate Driver Circuit With Threshold-Voltage-Shift Recovery and Synchronously Controlled Pull-Down Scheme

“…Voltage swing of the clock signals ranges from −10 to 30 V. Obviously, due to the lower operating duty ratio, the V TH shift of a TFT operated with a 25%-duty ac bias is less than that driven by a 33%-duty ac bias after a 3600-s effective stress. However, the V TH shift of the TFT under the 50%-duty reverse bias is only 5.4 V, which is smaller than those obtained from the 33%-duty and 25%-duty ac biases because the influence of charge trapping on the TFT is ameliorated [14]. Furthermore, because the TFT is operated with a low frequency, the times of the charging and discharging currents to parasitic capacitors are greatly diminished, resulting in the low power consumption.…”

“…The a-Si:H TFTs exhibit a low-field-effect mobility, making it difficult to charge the row lines in a panel quickly with large parasitic resistive and capacitive loadings [1]. Moreover, the instability of a-Si:H TFTs under the long-term operation and the bias stress causes severe threshold voltage (V TH ) shifts of the TFTs and limits, the reliability of gate driver circuits [14]- [17]. To deal with the above problems, Maurice et al [1] designed a simple a-Si:H gate driver circuit, in which the driving capability of the pull-up TFT (T3) is enhanced using the bootstrapping method; in addition, all of the TFTs are under very lowduty ratios to minimize the V TH shifts, as shown in Fig.…”