Installation and First Commissioning of the LLRF System for the European XFEL

Branlard, Julien; Ayvazyan, Gohar; Ayvazyan, V.; Butkowski, Łukasz; Cichalewski, W.; Czuba, Krzysztof; Fenner, Michael; Grecki, M.; Hierholzer, M.; Hoffmann, Matthias; Jatczak, Pawel; Killenberg, M.; Kostin, D.; Kühn, Daniel; Leśniak, Tomasz; Ludwig, Frank; Makowski, Dariusz; Makowski, Filip; Mavrič, Uroš; Mielczarek, Aleksander; Nawaz, Ayla; Oliwa, Krzysztof; Omet, Mathieu; Perek, Piotr; Pfeiffer, Sven; Pryschelski, Heinrich; Przygoda, Konrad; Rosner, Annika; Rybaniec, Radosław; Schlarb, H.; Schmidt, Christian; Shehzad, Nadeem; Sikora, Dominik; Szczepanski, Bartlomiej; Urbanski, Maciej; Varghese, G.; Weddig, Henning; Wedel, Robert; Wiencek, Mateusz; Wierba, Wojciech; Yang, Bin

doi:10.18429/jacow-ipac2017-thoaa3

Cited by 3 publications

(1 citation statement)

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“…With its modular and standardized nature, coupled with its flexibility, high performance, and exceptional reliability, MicroTCA.4 has gained increasing popularity in applications related to particle accelerators and high-energy physics experiments. Notably, it has found widespread usage at many large-scale scientific facilities such as LHC, European XFEL, ESS, and BESSY-II [7][8][9][10][11][12][13].…”

Section: Introductionmentioning

confidence: 99%

Design and development of MTCA.4-based generic control and data acquisition module for CSNS-II and SAPS-TP

Long,

Li,

Liu

et al. 2023

J. Inst.

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A new generation of domestically generic control and data acquisition AMC module has been developed to meet the requirements of the upgrade and renovation of the RCS LLRF system in the CSNS-II project, as well as the horizontal testing needs of the SAPS-TP. This module complies with the MicroTCA.4 standard and utilizes the Xilinx ZYNQ 7045 SOC as the core data processing chip. It can simultaneously run FPGA algorithms and the EPICS IOC remote control application program, serving as an autonomous control node. The module is equipped with 8 channels of 125 MSPS 16-bit ADC and 2 channels of 16-bit DAC with a maximum sampling rate of up to 500 MSPS. It also features standard expansion interface, front optical panel fiber interface, external clock interface, front panel digital IO interface, and more, catering to the needs of multiple systems in accelerator facilities such as radio-frequency, beam diagnostics, and control system. Additionally, the module can function independently for smaller-scale experimental and testing systems, such as the LLRF system for horizontal testing of SAPS-TP. To guarantee the seamless integration and proper operation of the AMC module within the MicroTCA.4 ecosystem, the MMC mezzanine card has been developed and thoroughly tested. In order to further reduce costs for small-scale systems, we optimized the software of the MMC so that the AMC board can run without the MCH module and realize self-health monitoring. For common applications, we have developed a complete software architecture and demo programs, including FPGA firmware, embedded Linux operating system, kernel driver modules, and EPICS IOC demo application programs. Detailed measurements have been conducted on hardware performance such as SNR, SFDR, channel isolation, as well as software performance including AXI DMA data bandwidth and system resources utilization, etc. The measurement results indicate that the module's performance indicators meet the design requirements.

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Section: Introductionmentioning

confidence: 99%