2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) 2019
DOI: 10.1109/norchip.2019.8906975
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Instruction Extension of a RISC-V Processor Modeled with IP-XACT

Saman Payvar
1
,
Esko Pekkarinen
2
,
Rafael Stahl
3
et al.
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Cited by 6 publications
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References 11 publications
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B-Box: An Efficient and Configurable RISC-V Bit Manipulation IP Generator

Sukumaran,
Babu,
Warrier
et al. 2024
Lecture Notes in Electrical Engineering
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B-Box: An Efficient and Configurable RISC-V Bit Manipulation IP Generator

Sukumaran,
Babu,
Warrier
et al. 2024
Lecture Notes in Electrical Engineering
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0
0
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Implementing Bit Manipulation Instructions on Architecture of RISC-V Processor

Devi,
Sreedhar
2023
2023 Global Conference on Information Technologies and Communications (GCITC)
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Implementation and Extension of Bit Manipulation Instruction on RISC-V Architecture using FPGA

B K,
B N,
P
et al. 2024
2024 5th International Conference on Circuits, Control, Communication and Computing (I4C)
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