Instruction fetch mechanisms for VLIW architectures with compressed encodings

Conte, Thomas M.; Banerjia, Sanjeev; Larin, Sergei Y.; Menezes, Kishore N.; Sathaye, Sumedh W.

doi:10.1109/micro.1996.566462

Cited by 36 publications

(23 citation statements)

References 16 publications

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“…Existing NOP compression techniques [Conte et al 1996;Jee and Palaniappan 2002] are irrelevant to the instruction bus width reduction. They also focus only on the code size reduction.…”

Section: Related Workmentioning

confidence: 99%

Reducing instruction bit-width for low-power VLIW architectures

Lee

Youn

Cho

et al. 2013

ACM Trans. Des. Autom. Electron. Syst.

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VLIW (very long instruction word) architectures have proven to be useful for embedded applications with abundant instruction level parallelism. But due to the long instruction bus width it often consumes more power and memory space than necessary. One way to lessen this problem is to adopt a reduced bit-width instruction set architecture (ISA) that has a narrower instruction word length. This facilitates a more efficient hardware implementation in terms of area and power by decreasing bus-bandwidth requirements and the power dissipation associated with instruction fetches. In practice, however, it is impossible to convert a given ISA fully into an equivalent reduced bit-width one because the narrow instruction word, due to bitwidth restrictions, can encode only a small subset of normal instructions in the original ISA. Consequently, existing processors provide narrow instructions in very limited cases along with severe restrictions on register accessibility. The objective of this work is to explore the possibility of complete conversion, as a case study, of an existing 32-bit VLIW ISA into a 16-bit one that supports effectively all 32-bit instructions. To this objective, we attempt to circumvent the bit-width restrictions by dynamically extending the effective instruction word length of the converted 16-bit operations. Further, we will show that our proposed ISA conversion can create a synergy effect with a VLES (variable length execution set) architecture that is adopted in most recent VLIW processors. According to our experiment, the code size becomes significantly smaller after the conversion to 16-bit VLIW code. Also at a slight run time cost, the machine with the 16-bit ISA consumes much less energy than the original machine.

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“…Existing NOP compression techniques [Conte et al 1996;Jee and Palaniappan 2002] are irrelevant to the instruction bus width reduction. They also focus only on the code size reduction.…”

Section: Related Workmentioning

confidence: 99%

Reducing instruction bit-width for low-power VLIW architectures

Lee

Youn

Cho

et al. 2013

ACM Trans. Des. Autom. Electron. Syst.

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“…• Stop-bits. A bit is reserved in each syllable, indicating whether it is the last syllable in a bundle or not, as presented in [11], [12], [13], [14], and [15]. However, none of the above-mentioned approaches are directly applicable to a dynamically reconfigurable VLIW processor.…”

Section: Related Workmentioning

confidence: 99%

“…The hardware required to fully support this can be quite complex. When every datapath needs to be able to accept an operation from any syllable slot in a bundle, a full crossbar is required [14]. Fortunately, the restrictions in the encoding scheme reduce this routing complexity to the diagram depicted in Fig.…”

Section: A Shared Requirementsmentioning

confidence: 99%

A sparse VLIW instruction encoding scheme compatible with generic binaries

Brandon

Hoozemans

Straten

et al. 2015

2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)

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Very Long Instruction Word (VLIW) processors are commonplace in embedded systems due to their inherent lowpower consumption as the instruction scheduling is performed by the compiler instead by sophisticated and power-hungry hardware instruction schedulers used in their RISC counterparts. This is achieved by maximizing resource utilization by only targeting a certain application domain. However, when the inherent application ILP (instruction-level parallelism) is low, resources are under-utilized/wasted and the encoding of NOPs results in large code sizes and consequently additional pressure on the memory subsystem to store these NOPs.To address the resource-utilization issue, we proposed a dynamic VLIW processor design that can merge unused resources to form additional cores to execute more threads. Therefore, the formation of cores can result in issue widths of 2, 4, and 8. Without sacrificing the possibility of code interruptability and resumption, we proposed a generic binary scheme that allows a single binary to be executed on these different issue-width cores. However, the code size issue remains as the generic binary scheme even slightly further increases the number NOPS. Therefore, in this paper, we propose to apply a well-known stop-bit code compression technique to the generic binaries that, most importantly, maintains its code compatibility characteristic allowing it to be executed on different cores. In addition, we present the hardware designs to support this technique in our dynamic core. For prototyping purposes, we implemented our design on a Xilinx Virtex-6 FPGA device and executed 14 embedded benchmarks. For comparison, we selected a nondynamic/static VLIW core that incorporates a similar stop-bit technique for its code compression.We demonstrate, while maintaining code compatibility on top of a flexible dynamic VLIW processor, that the code size can be significantly reduced (up to 80%) resulting in energy savings, and that the performance can be increased (up to a factor of three). Finally, our experimental results show that we can use smaller caches (2 to 4 times as small), which will further help in decreasing energy consumption.

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“…The tradeoff here is that as the compressed program becomes smaller, the Huffman decoder becomes larger. Their experiments are based on the TINKER EPIC Embedded architecture [34]. It is a 40-bit version of the HP PlayDoh VLIW machine specification adapted for embedded systems.…”

Section: B Code Compression For Vliw Architecturesmentioning

confidence: 99%

Code compression for embedded VLIW processors using variable-to-fixed coding

Xie

Wolf

Lekatsas³

2006

IEEE Trans. VLSI Syst.

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In embedded system design, memory is one of the most restricted resources, posing serious constraints on program size. Code compression has been used as a solution to reduce the code size for embedded systems. Lossless data compression techniques are used to compress instructions, which are then decompressed on-the-fly during execution. Previous work used fixed-to-variable coding algorithms that translate fixed-length bit sequences into variable-length bit sequences. In this paper, we present a class of code compression techniques called variable-to-fixed code compression (V2FCC), which uses variable-to-fixed coding schemes based on either Tunstall coding or arithmetic coding. Though the techniques are suitable for both reduced instruction set computer (RISC) and very long instruction word (VLIW) architectures, they favor VLIW architectures which require a high-bandwidth instruction prefetch mechanism to supply multiple operations per cycle, and fast decompression is critical to overcome the communication bottleneck between memory and CPU. Experimental results for a VLIW embedded processor TMS320C6x show that the compression ratios using memoryless V2FCC and Markov V2FCC are around 82.5% and 70%, respectively. Decompression unit designs for memoryless V2FCC and Markov V2FCC are implemented in TSMC 0.25-m technology.

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Instruction fetch mechanisms for VLIW architectures with compressed encodings

Cited by 36 publications

References 16 publications

Reducing instruction bit-width for low-power VLIW architectures

Reducing instruction bit-width for low-power VLIW architectures

A sparse VLIW instruction encoding scheme compatible with generic binaries

Code compression for embedded VLIW processors using variable-to-fixed coding

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