Instruction Scheduling for Dynamic Hardware Configurations

Panainte, Elena Moscu; Bertels, Koen; Vassiliadis, S.

doi:10.1109/date.2005.184

Cited by 17 publications

(23 citation statements)

References 8 publications

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“…Let us try to schedule the configuration prefetches for the three hardware modules on the given CFG. If we use the method developed by Panainte et al [PBV05], the result is shown in Figure 3.4b. As we can see, the load for M 3 can be propagated upwards in the CFG from node M 3 up to r. For nodes M 1 and M 2 it is not possible (according to this approach) to propagate their load calls to their ancestors, because they are in placement conflict.…”

Section: Motivational Examplementioning

confidence: 99%

“…To our knowledge, the works most closely related to our own, presented in Section 3.2, are [S + 10], [LH02] and [PBV05]. Panainte et al proposed both an intra-procedural [PBV05] and an inter-procedural [PBV06] static prefetch scheduling algorithm that minimizes the number of executed FPGA reconfigurations taking into account FPGA area placement conflicts.…”

Section: Static and Hybrid Configuration Prefetchingmentioning

confidence: 99%

“…Panainte et al proposed both an intra-procedural [PBV05] and an inter-procedural [PBV06] static prefetch scheduling algorithm that minimizes the number of executed FPGA reconfigurations taking into account FPGA area placement conflicts. In order to compute the locations in the control flow graph of an application where hardware reconfigurations can be anticipated, they first determine the regions of the graph not shared between any two conflicting hardware modules, and then insert prefetches at the beginning of each such region.…”

Section: Static and Hybrid Configuration Prefetchingmentioning

confidence: 99%

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Hardware/Software Codesign of Embedded Systems with Reconfigurable and Heterogeneous Platforms

Lifa¹

2015

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M odern applications running on today's embedded systems have very high requirements. Most often, these requirements have many dimensions: the applications need high performance as well as flexibility, energyefficiency as well as real-time properties, fault tolerance as well as low cost. In order to meet these demands, the industry is adopting architectures that are more and more heterogeneous and that have reconfiguration capabilities. Unfortunately, this adds to the complexity of designing streamlined applications that can leverage the advantages of such architectures.In this context, it is very important to have appropriate tools and design methodologies for the optimization of such systems. This thesis addresses the topic of hardware/software codesign and optimization of adaptive real-time systems implemented on reconfigurable and heterogeneous platforms. We focus on performance enhancement for dynamically reconfigurable FPGA-based systems, energy minimization in multi-mode real-time systems implemented on heterogeneous platforms, and codesign techniques for fault-tolerant systems.The solutions proposed in this thesis have been validated by extensive experiments, ranging from computer simulations to proof of concept implementations on real-life platforms. The results have confirmed the importance of the addressed aspects and the applicability of our techniques for design optimization of modern embedded systems. v vi Populärvetenskaplig Sammanfattning I dag är inbyggda system vanligt förekommande och deras antal fortsätter att öka. De används inom en mängd olika domäner, t.ex. hemelektronik, fordonsindustri, flygelektronik, medicin, etc., och de hittas nästan överallt omkring oss: från våra telefoner, bärbara datorer och tvättmaskiner till våra bilar. De applikationer som körs på dessa system har flera olika ökande krav: högprestanda, energieffektivitet, flexibilitet, feltolerans, realtidsegenskaper, och naturligtvis låg kostnad. För att kunna uppfylla dessa krav har industrin anammat arkitekturer som är mer och mer heterogena och som har omkonfigureringsmöjligheter. Olyckligtvis ökar detta komplexiteten när man ska utforma effektiva inbyggda system. I detta sammanhang blir det av yttersta betydelse att utveckla effektiva optimeringsmetoder och verktyg.Dagens applikationer består av en blandning av mjukvarukomponenter som har mycket olika energi-och prestandaegenskaper beroende på vilka hårdvaruenheter där de körs på, vilket gör dem lämpliga för heterogena plattformar. En heterogen plattform består av olika typer av hårdvaruen-heter, var och en med sina egenskaper, som riktar sig till vissa tillämpn-ingsområden. Under det senaste decenniet har utvecklingen av rekonfigurerbara hårdvarutekniker accelererat, vilket bidrar till den ökande populariteten för fältprogrammerbara grindmatriser (FPGA). Idag, ger hård-varutillverkare stöd för partiell dynamisk omkonfigurering; detta innebär att delar av en FPGA kan konfigureras vid run-time, medan andra delar förblir fullt fungerande. Dessa tekniska framsteg har...

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Section: Motivational Examplementioning

confidence: 99%

Section: Static and Hybrid Configuration Prefetchingmentioning

confidence: 99%

Section: Static and Hybrid Configuration Prefetchingmentioning

confidence: 99%

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Hardware/Software Codesign of Embedded Systems with Reconfigurable and Heterogeneous Platforms

Lifa¹

2015

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“…II-A), makes the on-line approach feasible. The execution of M i is done in hardware or in software (lines [11][12][13][14], depending on the run-time conditions. Once the execution of M i finishes, we save its timestamp and then we compute the estimated performance gains G kMi (line 17) for all the modules currently recorded in the hardware history register HW (line 16).…”

Section: The Priority Function γ Mkmentioning

confidence: 99%

“…Many static algorithms for prefetching were proposed: [9], [12], [17], [10]. All share one limitation: in case of nonstationary behavior, they are unable to adapt, since the prefetch schedule is fixed based on average profiling information.…”

Section: Introduction and Related Workmentioning

confidence: 99%

Dynamic Configuration Prefetching Based on Piecewise Linear Prediction

Lifa

Eles

Peng

2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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Abstract-Modern systems demand high performance, as well as high degrees of flexibility and adaptability. Many current applications exhibit a dynamic and nonstationary behavior, having certain characteristics in one phase of their execution, that will change as the applications enter new phases, in a manner unpredictable at design-time. In order to meet the performance requirements of such systems, it is important to have on-line optimization algorithms, coupled with adaptive hardware platforms, that together can adjust to the run-time conditions. We propose an optimization technique that minimizes the expected execution time of an application by dynamically scheduling hardware prefetches. We use a piecewise linear predictor in order to capture correlations and predict the hardware modules to be reached. Experiments show that the proposed algorithm outperforms the previous state-of-art in reducing the expected execution time by up to 27% on average.

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